Exhibit 99.4

EUV Products and Business Opportunity Christophe Fouquet Executive Vice President Business Line EUV

EUV products and business opportunity Key messages Slide 2 29 Sept. 2021 ASML EUV lithography extends our Logic and DRAM customers roadmap by providing lithography resolution improvement, state of the art overlay performance and year on year cost reduction Our customers are using EUV in Logic node and starting to use EUV in DRAM node in 2021. EUV layers adoption continues to grow to reduce patterning complexity and cost ASML EUV capability ramp combined with its productivity roadmap expected to support our customers surging demand in the coming years EUV product roadmap expected to extend our EUV platform and introduce EUV 0.55 NA platform in parallel to provide comprehensive and flexible solutions to our customers’ continuous demand for patterning scaling well into the next decade We expect to continue to improve EUV profitability over time through the combined execution of our value enhancing product roadmap and ambitious systems and service cost reduction roadmap Public

EUV 0.33 NA is in production for both Logic and DRAM, and its adoption is expected to continue to grow EUV 0.33 NA extension and EUV 0.55 NA introduction is expected to extend EUV values to the next decade Our increased EUV product and service value is expected to continue to drive profitability

EUV 0.33 NA is in production, for both Logic and DRAM All advanced semiconductor manufacturers expected to run EUV in Slide 4 29 Sept. 2021 production by 2024 Fastest, Largest-capacity Mobile Memory Based on today’s most advanced (1z) process node, Samsung’s new 16Gb LPDDR5 is the first memory to be mass produced using EUV technology, providing the highest speed and largest capacity available in mobile DRAM. Source: Samsung, press release, Korea August 30, 2020 Source: Apple, press release, November 10, 2020 SK Hynix starts Mass production of 1anm DRAM using EUV Equipment SK Hynix, Seoul, July 12, 2021 Micron announces EUV fabs by 2024 Source: Intel, Pat Gelsinger, “Engineering the future”, March 23, 2021 Source:The Register, Jul 2021 Public

EUV 0.33 NA adoption enabled by platform maturity in high-volume manufacturing Slide 5 29 Sept. 2021 100% 3000 System output 95% Max wafers per day (single system, weekly average) 2500 Installed base system availability 90% day 4 weeks moving average (end of period) 85% 2000 per 80% 75% 1500 Availability Wafers 70% 1000 65% 60% 500 55% 50% 0 2017 2018 2019 2020 2021 ASML commitment is expected to bring EUV availability >95% and increase wafer per day output >50% by 2025 Source : ASML installed base data Public

EUV 0.33 NA adoption expected to continue for Logic and DRAM to support most advanced device roadmap Slide 6 29 Sept. 2021 30 Actuals Today Roadma 20 Logic exposures Memory of max min Number 10 0 2018 2019 2020 2021 2022 2023 20242025 Public

EUV increased adoption expected to result into >2x increase of EUV wafer moves per year 2025 compared to 2021 Slide 7 29 Sept. 2021 800% 30 Actuals Today Roadmap (ambition) year Memory per 20 Logic exposed exposures Memory of max wafers min 10 EUV Number Logic Total 100% 0 2018 2019 2020 2021 2022 2023 2024 2025 Public    

ASML to address EUV demand by increasing shipments and system productivity Slide 8 29 Sept. 2021 Actuals Today Roadmap 400% (ambition) [#] year wph*] 300% per[ put Through 200% ents/Capacity Shipm System |100% 2018 2019 2020 2021 2022 2023 2024 2025 NXE:3400B NXE:3400C NXE:3400C NXE:3600D NXE:3600D NXE:3800E NXE:3800E NXE:4000F *wph = wafers per hour Public

ASML to address EUV demand by increasing shipments and system productivity Slide 9 29 Sept. 2021 800% Actuals Today Roadmap (ambition) 700% year [#] Fab Model: EUV estimated (3600D) wph] x Fab Capacity Exposures System Memory per 600% year (kwspm*) per fab wph] [units per[ 45 10-20 9-18 Logic put 500% exposed Memory capacity 400% 100 1-6 2-9 Through wafers 300% wafer ents/Capacity EU EUV Shipm System 200% 100%* Logic Total 2018 2019 2020 2021 2022 2023 2024 2025 NXE:3400B NXE:3400C NXE:3400C NXE:3600D NXE:3600D NXE:3800E NXE:3800E NXE:4000F * 2018 reference=100% Public    

Higher than previously projected DRAM adoption will be an additional driver for EUV demand Slide 10 29 Sept. 2021 800% Actuals Today 700% year Memory per 600% 500% exposed 400% wafers 300% EUV 200% Logic Total 100% 2018 2019 2020 2021 2022 2023 2024 2025 Public

EUV reduces lithography and process steps resulting in significant defect, cost and cycle time reduction Slide 11 29 Sept. 2021 No EUV – EUV (0.33 NA) Critical Total 120% litho masks process steps # Process stepsNo EUV No EUV 100% No EUV EUV (0.33 NA) EUV 80% (0.33 NA) EUV (0.33 NA) 60% EUV value to customers 40% No EUV Less defects 20% EUV based Cost reduction 0% Shorter cycle time Node (DRAM) Public    

Samsung reported >20% defect reduction at EUV introduction versus multi-patterning immersion (ArFi) Slide 12 29 Sept. 2021 Eliminating multi-patterning related defects Defects ratio Patterning ArFi MPT EUV SET> 20% DRAM D1xBLP [%] SEM Image ration Defects Enhancing patterning precision and cost BLP ArFi MPT EUV SET ArFi EUV Reducing number of steps and accumulated defects Source: Samsung investor Forum, November 2020 Public

EUV is in production for both Logic and DRAM, and its adoption is expected to continue to grow EUV extension and EUV 0.55 NA introduction is expected to extend EUV values to the next decade Our increased EUV product and service value is expected to continue to drive profitability

ASML is expected to continue to extend DUV and EUV platforms at the pace required by our customers Slide 14 29 Sept. 2021 mWavelength NA, Half pitch 2020 2021 2022 2023 2024 ³2025 DUV NXT:2000i NXT:2050i NXT:2100i NEXT 1.35 NA, 38 nm 2.0 nm | 275wph 1.5 nm | 295wph 1.3 nm | 295wph (ArFi) NXE:3400C NXE:3600D NXE:3800E NXE:4000F EUV 0.33 NA, 13 nm 2 3 3 <0.8 nm | >220wph 1.5 nm | 135 wph / 145wph 1.1 nm | 160wph <1.1 nm | >195wph / 220wph wafers/hours (wph) are based on 30mJ/cm² 1) 185wph@20mJ/cm² 2) 170wph@20mJ/cm² 3) Throughput upgrade Product: Matched Machine Overlay (nm)|Throughput(wph) Product status Released Development Definition Public

EUV 0.55 NA is expected to be added to EUV portfolio to support high-volume manufacturing in 2025—2026 Slide 15 29 Sept. 2021\ Wavelength NA, Half pitch 2020 2021 2022 2023 2024 ³2025 NXE:3400C NXE:3600D NXE:3800E NXE:4000F 0.33 NA, 13 nm 2 3 3 <0.8 nm | >220wph 1.5 nm | 135 wph / 145wph 1.1 nm | 160wph <1.1 nm | >195wph / 220wph Early Access Customer Customer EUV Customer timing 0.55 NA ASML R&D HVM EXE:5000 EXE:5000 EXE:5200 0.55 NA, 8 nm 1 at ASML fab <1.1 nm | 150wph <0.8 nm | 220wph EUV 0.55 NA higher resolution enables 1.7x smaller features and 2.9x increased density wafers/hours (wph) are based on 30mJ/cm² EUV 0.55 NA higher imaging contrast 1) 185wph@20mJ/cm2 2) 170wph@20mJ/cm² enables 40% improvement in local CDU 3) Throughput upgrade and improves productivity on critical layers Product: Matched Machine Overlay (nm)|Throughput(wph) Product status Released Development Definition Public

EUV 0.55 NA expected to once again reduce litho and process steps at the horizon of 2025—2026 for both Logic and DRAM Slide 16 29 Sept. 2021 Critical litho masks Total process steps EUV value to customers 120% EUV EUV Less defects No EUV (0.33 NA) No EUV (0.33 NA) 100% EUV EUV Cost reduction (0.33 NA) (0.55 NA) EUV 80% EUV (0.55 NA) (0.33 NA) Shorter cycle time 60% m40% 20% No EUV 0% EUV (0.33 NA) EUV (0.55 NA) 2021 2025-2026 2021 2025-2026 DRAM expectations DRAM expectations Public

EUV 0.55 NA is an evolutionary step on EUV technology, we have the source, we developed new optics Slide 17 29 Sept. 2021 NXT EUV 0.33 NA EUV 0.55 NA System changes platform to platform High 193 nm deep UV light 13.5 nm EUV light 13.5 nm EUV light Source Many Existing changes technology Source: different interface Low High Atmospheric condition Vacuum condition Vacuum condition Many Existing Scanner changes technology Higher acceleration/speed stages Low High Transmissive optics Reflective optics Reflective optics Many Anamorphic mirrors with Optics New optics changes more accuracy Low Public

A large part of our EUV 0.55 NA platform is expected to be common with our EUV 0.33 NA reducing introduction risk, cost and R&D Slide 18 29 Sept. 2021 RETICLE HANDLING RETICLE STAGE PROJECTION OPTICS BOX ILLUMINATION SOURCE WAFER HANDLING WAFER STAGE DRIVE LASER Specific Common Public

EUV optical projection mirrors ASML and Zeiss cooperation on mirror design and unique metrology system Slide 19 29 Sept. 2021 EUV 0.55 NA mirror metrology fully operational at Zeiss Public

EUV optical projection mirrors Mirrors of unprecedented size and accuracy Slide 20 29 Sept. 2021 EUV 0.55 NA optics: 1m diameter with accuracy of 20pm If you were to enlarge these mirrors to the size of planet Earth, the biggest aberration would be the diameter size of a human hair Public

Facilities for integration of EUV 0.55 NA in progress Slide 21 29 Sept. 2021 Cleanroom, Fab ASML Veldhoven Public

EUV 0.55 NA manufacturing is expected to improve quality and cycle time through integrations of 4 pre-qualified modules Slide 22 29 Sept. 2021 Pre-qualified module: RETICLE Pre-qualified Pre-qualified module : OPTICS module: SOURCE Pre-qualified module : WAFER Integration is now ongoing at ASML for all 4 pre-qualified modules RETICLE OPTICS WAFER SOURCE SOURCE SOURCE Top Frames, Wilton Integration, Oberkochen Metro frame, Veldhoven Optical Platform, San Diego Drive Laser, Veldhoven Vessel, San Diego Public

EUV is in production for both Logic and DRAM, and its adoption is expected to continue to grow EUV extension and EUV 0.55 NA introduction is expected to extend EUV values to the next decade Our increased EUV product and service value is expected to continue to drive profitability

Increased EUV product and service value combined with Slide 24 cost reduction expected to drive better profitability 29 Sept. 2021 400% Actuals Today Roadmap 300% day** per ghput 200% 2 nm wafer[nm] throu rlay Average stem 100% 1 nm Ove Sy 2018 2019 2020 2021 2022 2023 2024 2025 NXE:3400B NXE:3400C NXE:3400C NXE:3600D NXE:3600D NXE:3800E NXE:3800E NXE:4000F* Normalized with 2018 and based on 30 mJ Public

EUV products and business opportunity Key messages Slide 25 29 Sept. 2021 ASML EUV lithography extends our Logic and DRAM customers roadmap by providing lithography resolution improvement, state of the art overlay performance and year on year cost reduction Our customers are using EUV in Logic node and starting to use EUV in DRAM node in 2021. EUV layers adoption continues to grow to reduce patterning complexity and cost ASML EUV capability ramp combined with its productivity roadmap expected to support our customers surging demand in the coming years EUV product roadmap expected to extend our EUV platform and introduce EUV 0.55 NA platform in parallel to provide comprehensive and flexible solutions to our customers’ continuous demand for patterning scaling well into the next decade We expect to continue to improve EUV profitability over time through the combined execution of our value enhancing product roadmap and ambitious systems and service cost reduction roadmap Public

Forward Looking Statements Slide 26 29 Sept. 2021 This presentation contains statements that are forward-looking, including statements with respect to expected industry and business environment trends including expected growth, outlook and expected financial results, including expected net sales, gross margin, R&D costs, SG&A costs and effective tax rate, annual revenue opportunity for 2025, financial model for 2025 and assumptions and expected growth rates and drivers, expected growth including growth rates 2020-2025 and 2020-2030, total addressable market, growth opportunities beyond 2025 and expected annual growth rate in lithography and metrology and inspection systems and expected annual growth rate in installed base management, expected trends in addressable market up to 2030, expected trends in Logic and Memory revenue opportunities, long term growth opportunities and outlook, expected trends in demand and demand drivers, expected benefits and performance of systems and applications, semiconductor end market trends, expected growth in the semiconductor industry including expected demand growth and capital spend in coming years, expected wafer demand growth and investments in wafer capacity, expected lithography market demand and growth and spend, growth opportunities and drivers, expected trends in EUV and DUV demand, sales, outlook, roadmaps, opportunities and capacity growth and expected EUV adoption, profitability, availability, productivity and output and estimated wafer demand and improvement in value, expected trends in the applications business, expected trends in installed base management including expected revenues and target margins, expected trends and growth opportunity in the applications business, expectations with respect to high-NA, the expectation of increased output capacity, plans, strategies and strategic priorities and direction, expectation to increase capacity, output and production to meet demand, the expectation that Moore’s law will continue and Moore’s law evolution, product, technology and customer roadmaps, and statements and intentions with respect to capital allocation policy, dividends and share buybacks, including the intention to continue to return significant amounts of cash to shareholders through a combination of share buybacks and growing annualized dividends and statements with respect to ESG commitment, sustainability strategy, targets, initiatives and milestones. You can generally identify these statements by the use of words like “may”, “will”, “could”, “should”, “project”, “believe”, “anticipate”, “expect”, “plan”, “estimate”, “forecast”, “potential”, “intend”, “continue”, “target”, “future”, “progress”, “goal” and variations of these words or comparable words. These statements are not historical facts, but rather are based on current expectations, estimates, assumptions and projections about our business and our future financial results and readers should not place undue reliance on them. Forward-looking statements do not guarantee future performance and involve a number of substantial known and unknown risks and uncertainties. These risks and uncertainties include, without limitation, economic conditions; product demand and semiconductor equipment industry capacity, worldwide demand and manufacturing capacity utilization for semiconductors, semiconductor end-market trends, the impact of general economic conditions on consumer confidence and demand for our customers’ products, performance of our systems, the impact of the COVID-19 outbreak and measures taken to contain it on the global economy and financial markets, as well as on ASML and its customers and suppliers, and other factors that may impact ASML’s sales and gross margin, including customer demand and ASML’s ability to obtain supplies for its products, the success of R&D programs and technology advances and the pace of new product development and customer acceptance of and demand for new products, production capacity and our ability to increase capacity to meet demand, the number and timing of systems ordered, shipped and recognized in revenue, and the risk of order cancellation or push out, production capacity for our systems including the risk of delays in system production and supply chain capacity, constraints, shortages and disruptions, trends in the semi-conductor industry, our ability to enforce patents and protect intellectual property rights and the outcome of intellectual property disputes and litigation, availability of raw materials, critical manufacturing equipment and qualified employees and trends in labor markets, geopolitical factors, trade environment; import/export and national security regulations and orders and their impact on us, ability to meet sustainability targets, changes in exchange and tax rates, available liquidity and liquidity requirements, our ability to refinance our indebtedness, available cash and distributable reserves for, and other factors impacting, dividend payments and share repurchases, results of the share repurchase programs and other risks indicated in the risk factors included in ASML’s Annual Report on Form 20-F for the year ended December 31, 2020 and other filings with and submissions to the US Securities and Exchange Commission. These forward-looking statements are made only as of the date of this document. We undertake no obligation to update any forward-looking statements after the date of this report or to conform such statements to actual results or revised expectations, except as required by law. Public

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