Exhibit 99.3

Technology Strategy to Drive
Moore’s Law into
Next Decade
Martin van den Brink
President and
Chief Technology Officer

Technology strategy    
Holistic Lithography roadmap is driven by our unique
Key messages     patterning control solutions that deliver customer value viaSlide 2
29 Sept. 2021
improved on product performance.
• Moore’s Law is alive and well! Industry innovation    • ASML’s comprehensive product portfolio is aligned to our
continues, fueled by system scaling, delivering highly valued     customers’ roadmaps, delivering cost effective solutions in support
semiconductor products.     of all applications from leading edge to mature nodes
• Semiconductor system scaling enables exponential    • Our next generation EUV technology, High-NA, is progressing
performance improvement and energy reduction in support of     well and will be the engine to drive the lithography roadmap into
significant growth of data exchange.     the next decade
• Customers’ roadmaps require continued shrink and    • Continued execution of our strategic priorities is expected to
reduction in edge placement error to drive affordable scaling     provide cost effective solutions for our customers, enable the
into next decade.     extension of the industry roadmap into the next decade, and
support our long-term sustainability commitment
2

• Moore’s Law evolution and customer roadmap
ASML’s strategic priorities
3

Significant device innovation in logic ahead of us    
scaling roadmap continues to 1 nm and beyond     Slide 4
29 Sept. 2021
3 nm     2 nm1,5 nm1 nm and beyond
PP: 44-48, MP: 21-24     PP: 40-44, MP: 18-21PP: 40-44, MP: 18-21PP: 38-42, MP: 15-18
BPR    BPR
FinFET    Nanosheets, BPR Forksheets, VHV std cell arch. CFET, BEOL w/airgaps 2D atomic channels
5T     5T <5T4T<4T
Buried power rail (BPR)    Nanosheets Forksheets Metal etch w/ airgaps Metal etch w/ airgaps
PP: Poly Pitch (nm)
MP: dense metal pitch (nm)
VHV: Vertical-Horizontal-VerticalCFET: Complementary FET
Source: IMEC, Sri Samavedam, “Future logic scaling: Towards atomic channels and deconstructed chips”, IEDM, December 2020.     Public
4

Innovation is not limited to device level    
TSMC’s system roadmap to >300 B transistors     Slide 5
29 Sept. 2021
WoW: Wafer on Wafer    CoWoS: Chip on Wafer on Substrate HBM: 3D High Speed MemoryRDL: Re Distribution Layer
SOC: System on Chip    CoW: Chip on Wafer FPGA: Field Programmable Grid ArrayInFo: Integrated Fan-Out SoIC: System on Integrated Chips
> 300 BTSMC—SoIC™ï¸
transistors
InFo    150B
transistors
CoWos    
>50 B
15Btransistors
transistors
7B    
transistors    
200 MOS transistors    
A few transistors    
3D FinFET New channel materials
HKMG     2P2EEUV
Immersion     ELKMetal oxide ESL
SiGe    Low-R Barrier Self-aligned line w/ flexible space
Cu/LowK    Co Capliner Low damage/hardening low-k & novel Cu fill
Source: Mark Liu, TSMC, “Unleash the future of innovation” ISSCC, Feb 15, 2021     Public
5

Innovation is not limited to device level    
TSMC’s system roadmap to >300 B transistors     Slide 6
29 Sept. 2021
WoW: Wafer on Wafer    CoWoS: Chip on Wafer on Substrate HBM: 3D High Speed MemoryRDL: Re Distribution Layer
SOC: System on Chip    CoW: Chip on Wafer FPGA: Field Programmable Grid ArrayInFo: Integrated Fan-Out SoIC: System on Integrated Chips
Device scaling (Including foundry supply chain)     TSMC—SoIC™ï¸
Circuit scaling (Including foundry customers)    
Dimensional scaling (Including litho supply chain)    InFo
Architectural scaling by foundry customers    
CoWos    
Chip level towards
system level
3D FinFET New channel materials
HKMG     2P2EEUV
Immersion     ELKMetal oxide ESL
SiGe     Low-R BarrierSelf-aligned line w/ flexible space
Cu/LowK     Co Capliner Low damage/hardening low-k & novel Cu fill
Source: Mark Liu, TSMC, “Unleash the future of innovation” ISSCC, Feb 15, 2021     Public
6

Moore’s Law evolution: the next decade    
Traditional scaling metrics like clock frequency have been saturated since 2005    Slide 7
29 Sept. 2021
Public dataCustomerSpeculation
1020     projection
Dennard Post Dennard
1018     scaling scaling
1016    
1014    
1012    
1010    
108    
106    
104     Clock Frequency1
[MHz]
102    
1    
1970    1980 19902000201020202030
Source: ¹Karl Rupp as published by: Shekar Bokar, QUALCOMM, “Future of computing in the so-called post Moore’s Law era”, International conference    
for high performance computing, networking storage and analysis, November 18, 2020.     Public
7

Moore’s Law evolution: the next decade    
Scaling metric of transistor and litho density continues in this decade    Slide 8
29 Sept. 2021
Public dataCustomerSpeculation
1020     projection
DennardPost Dennard
1018     scalingscaling
1016    
1014    
1012    
1010     Transistor density2
[#/mm2]
108     Device and layout
optimizationLitho density2
106     (Contact Poly Pitch*Metal Pitch)-1
[109/mm2]
104     Clock Frequency1
[MHz]
102    
1    
1970    1980 19902000201020202030
Sources: ¹Karl Rupp 2ASML data and projection using Rupp     Public
8

Moore’s Law evolution: the next decade    
A system metric measuring energy and time efficiency combined    Slide 9
29 Sept. 2021
Energy-Efficient Performance for systems and devices defined as
[1/J.s]
If applied per single device:
EEP = fc /e
fc = clock frequency [s-1]
e = the transistor switch energy [J]
Using the Dennard¹ scaling model, when the dimension scales with k-1, frequency with k,
area with k-² and power density constant, it follows:    
EEP on-device level scales with k4
If density (~k2) scales 2x every 2 year, then EEP (~k4) scales 4x every 2 year
1Source: Robert H. Dennard et al. “Design of ion implanted MOSFET’s with very small physical dimensions”, IEEE Journal of solid-state circuits, vol SC 9, October 1973, pp. 256-268.    Public
9

Moore’s law evolution: the next decade    
Device Energy Efficient    Performance growth been saturated since 2005 Slide 10
29 Sept. 2021
Public dataCustomerSpeculation
1020     projection
DennardPost DennardSystem Energy
1018     scalingscaling Efficient Performance3
[1/J.s]
1016     From transistor to
system scaling
1014     Transistor Energy
Efficient Performance2
1012     [[1/J.s]
1010     Transistor density2
[#/mm2]
108     Device and layout
optimizationLitho density2
106     (Contact Poly Pitch*Metal Pitch)-1
[109/mm2]
104     Clock Frequency1
[MHz]
102    
1    
1970    1980 199020002010202020302040
Sources: ¹Karl Rupp, 2 ASML data and projection using Rupp     Public
10

Moore’s Law evolution: the next decade    
System Energy Efficient Performance growth 3x/2yrs continues    to 2040Slide 11
29 Sept. 2021
Source: TSMC, Mark Liu, “Unleash the future of innovation” ISSCC, Feb 15, 2021.     Public
11

Moore’s law evolution: the next decade    
From cost per transistor through density, to cost of time and energy through systems    Slide 12
29 Sept. 2021
1020     Energy
1018     Performance3
1016    
1014     tor Energy
Performance2
1012    
1010     tor density2
108     Device and layout
optimizationLitho density2
106     (Contact Poly Pitch*Metal Pitch)-1
[109/mm2]
104     Clock Frequency1
[MHz]
102    
1    
1970    1980 199020002010202020302040
Sources: ¹Karl Rupp, 2ASML data and projection using Rupp, 3Mark Liu, TSMC, normalized to transistor EEP in 2005.     Public
12

Moore’s law evolution: the next decade    
System scaling to satisfy the need for performance and energy consumption    Slide 13
29 Sept. 2021
1020    
System improvements    System System Energy
Efficient Performance3
1018    dominated by Transistor scaling scaling [1/J.s]
1016     From transistor to
system scaling
1014     Transistor Energy
Efficient Performance2
1012     [[1/J.s]
1010     Transistor density2
[#/mm2]
108     Device and layout
optimizationLitho density2
106     (Contact Poly Pitch*Metal Pitch)-1
[109/mm2]
104     Clock Frequency1
[MHz]
102    
1    
1970    1980 199020002010202020302040
Sources: ¹Karl Rupp, 2ASML data and projection using Rupp, 3Mark Liu, TSMC, normalized to transistor EEP in 2005.     Public
13

AMD 3D chiplet gives an 3.1-3.8 EEP improvement    
By integrating memory with the processor in one package    Slide 14
29 Sept. 2021
3x power reduction,    
4-25% speed improvement    
Structural silicon    
64MB L3 cache die    
Direct copper-to-copper bond    
Through Silicon Vias (TSVs) for    
silicon-to-silicon communication    
Up to 8-core “Zen 3” CCD    
“Accelerating the ecosystem”, Compute    
14

Moore’s law evolution: the next decade    
System scaling to satisfy the need for performance and energy consumption    Slide 15
29 Sept. 2021
Public dataCustomerSpeculation
1020     projection
System improvements    System System Energy
EfficientPerformance3
1018    dominated by Transistor scaling scaling [1/J.s]
1016     From transistor to
system scaling
1014     Transistor Energy
EfficientPerformance2
1012     [[1/J.s]
1010     Transistor density2
[#/mm2]
108     Device and layout
optimizationLitho density2
106     (Contact Poly Pitch*Metal Pitch)-1
[109/mm2]
104     Clock Frequency1
[MHz]
102    
1    
1970    1980 199020002010202020302040
Sources: ¹Karl Rupp, 2ASML data and projection using Rupp, 3Mark Liu, TSMC, normalized to transistor EEP in 2005.     Public
15

Litho density scaling continues    in this decade
Overlay and Optical Proximity Correction    errors shrink aggressively Slide 16
29 Sept. 2021
2x every 6 years    
Source: Average customer roadmap extended by ASML extrapolation May 2021, averaged with 2020 IRDS Roadmap Mustafa Badaroglu,    
“IRDS IFT – More Moore Spring meeting, IEEE, April 21, 2020     Public
16

Memory roadmap    for the nextdecade
DRAM scaling below 10 nm and NAND    stacking continues > 600 layers Slide 17
29 Sept. 2021
DRAM    
After 10 years     NowChallenge<10 nm
1y    1z 1a1b1c1d0a
NAND    
After 10 years     NowChallenge>600layers
96    128 1762xx3xx4xx5xx6xx
Source: Sk hynix, S.H.Lee, “Memory’s journey towards the future ITC world, IEEE IRPS 21 March 21, 2021     Public
17

Projection of    lithography layers by technology
Slide 18
29 Sept. 2021
KrF
Logic     Layer stack
5 nm    3 nm 2 nm~1.5 nm1 nm
KrF
DRAM     EUV – High-NA
Layer stack
1A    1B 1C0A0BEUV
ArFi
ArF
KrF
KrF I-Line
3D-NAND     Layer stack
176L    2xxL 3xxL4xxL5xxL
2021     ~2030
Source: ASML Corporate Strategy and Marketing estimates     Public
18

Projection of lithography    layers by technology
Lithography layer count grows, driven by DUV and EUV     Slide 19
29 Sept. 2021
KrF
Logic     Layer stack
5 nm    3 nm 2 nm~1.5 nm1 nm
KrF
DRAM     EUV – High-NA
Layer stack
1A    1B 1C0A0BEUV
DUV
KrF
3D-NAND     Layer stack
176L    2xxL 3xxL4xxL5xxL
2021     ~2030
Source: ASML Corporate Strategy and Marketing estimates     Public
19

Semiconductor and shrink roadmap: the next decades
Slide 20
29 Sept. 2021
In the next decade, system scaling continues to fuel the need
10âµ    
1962    of advanced semiconductor solutions where litho shrink
component 10â´     remains key to improving circuit density and cost.
per    1965
cost 10³    
10²     1970
manufacturing     Implications for ASML
Relative 10     The shrink roadmap requires innovation to improve litho
1     performance at lower cost and higher productivity.
1    10 10² 10³10â´ 10âµ
Number of components per integrated circuit
We continue to safeguard our approach by developing trusting
relationships with customers, with stronger holistic products.
20

Moore’s Law evolution and customer roadmap
• ASML’s strategic priorities
21

ASML’s strategic priorities    
Slide 22
29 Sept. 2021
Strengthen    â–ª Enhance execution capabilities to deliver performance, cost
customer trust     and robustness to customers needs
Holistic litho and    â–ª Build a leading position in edge placement error
applications    
DUV    â–ª Drive DUV performance and market share
competitiveness    
EUV    
industrialization    â–ª EUV high-volume production performance, ramp and support
High-NA    â–ª Enable litho simplification for future nodes
Public
22

Our holistic portfolio    is more important than ever
Lithography scanner with Slide 23
29 Sept. 2021
advanced control capability
Etch and
deposition tools
Process window     Process window
Prediction and     Control
Enhancement    
Optical proximity correction     ieldStar E-beam
Computational lithography     Optical metrology
computational metrology     E-beam metrology
E-beam inspection
Process window
Detection
Public
23

Our    holistic portfolio ismore importantthanever
Slide 24
29 Sept. 2021
EUV     DUV
High-NA    
Applications
Public
24

Applications: strategic directions    
Deliver leading solutions for optical and e-beam metrology and inspection    Slide 25
APPS     29 Sept. 2021
Customer Value     ASML Apps product roadmap
Capturing more wafer signatures to    • Productivity
improve robust on-wafer process control    • Robust alignment schemes
Nanometers    
Tighter process capabilities    • Single Beam resolution and applications
3→6 sigma control    • Edge Placement Error control
• Free-Form OPC and Machine Learning
Good wafers    Capturing small defects for •Multibeam resolution
per day per    yield of advanced nodes •Computationally guided inspection
unit cost    
More measurements at fixed    • Productivity/multibeam
metrology & inspection budget    • E-beam platform consolidation
• OPC accuracy, speed and user-friendliness
Faster time-to-solution    
Time to yield     •Single process control platform and analytics
Public
25

E-beam inspection has inherent resolution advantage    
Increasing throughput through increasing parallelism with multibeam     Slide 26
APPS     29 Sept. 2021
1000000 Min defect size for
2 nm node and below
100000 Optical
Bright Field
10000 Inspection
1000 Gen 3 Multibeam (~2028)
100 Increased
[mm²/hr]     throughput
enables
10 additional HVMGen 2 Multibeam (~2024)
ghput     applications
Throu    1
0.1 Gen 1 Multibeam (2021)
0.01 Scanning
electron
microscope
0.001 imageSingle e-beam (R&D)
0.0001
60 40201086421
Defect size [nm]Public
26

Metrology, Inspection & Patterning Control Roadmap    
Slide 27
APPS     29 Sept. 2021
2020    2021 202220232024³ 2025
Scanner Interfaces    
and Control Software     Increasing Scanner Actuation (DUV and EUV), EPE Control
Overlay Metrology     Fast Stages, Multiple Wavelengths, Computational Metrology,
YieldStar     In-Device Metrology
E-beam    eP5 0.1nm precision, 12umSinglefield of vi w, Beam9K V HLE (option)High Resolution, LargeeP6FieldHigh r Precision,of View,High r Resolution eP7 Next Generation
Metrology     Massive Metrology, EPE metrologyeP7XLE
eP5XS 18.5KeV landing energy    eP5XLE 30KeV landing energy
50KeV landing energy
E-Beam Defect    
Inspection     Multi-beam, Fast and Accurate Stages, High Landing Energy, Guided Inspection
Computational     Improved Model Accuracy, Inverse OPC,
Lithography     Machine and Deep Learning, Etch Models
Public
27

NXT:2050i in volume manufacturing at customers    
DUV    20% overlay improvement, faster reliability and productivity ramp-up Slide 28
29 Sept. 2021
NXT:2050i
Matched machineDedicated chuck
overlay ~1.2 nmoverlay ~0.8 nm
6000    5,000 wafers per day in 18 days 200180 hours reliability in 13 weeks
180
5000    NXT:2050i 160NXT:2050i
Faster ramp 140Higher availability
4000    
120
per day     (hours)
3000     100
Wafers     MTBI 80
2000    
60
40
1000    
20
0     0
1 2 3    4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 NXT:2000i1 2 3 4 5 6 7 8 9 1011 12 13 14 15 16 1718 19
Days after completing installation Weeks after completing installation
NXT:2050iPublic
28

DUV: Strategic directions    
DUV    Deliver leading solutions for advanced capabilities and higher productivity Slide 29
29 Sept. 2021
Customer value ASML DUV product roadmap
Overlay    Improve overlay (stability) especially •NXT:2100i with optics and alignment improvements
for matching to EUV
Productivity &    More good wafers per day at •Immersion productivity increase through
Availability    lower cost per wafer higher scan speed
•XT to NXT transition for dry lithography
Installed base    Cost-competitive service offerings for •Productivity Enhancement Packages for installed base
entire product lifecycle •Value added service solutions increasing availability at
node performance
New markets    Productivity and overlay performance for •Mature XT platform with application specific options
specific applications •Extend i-line product portfolio for Mature markets (>40nm)
•Fab replacement solutions
Circular    Sustainable product & service offerings •System Node Extension Package roadmap
economy     •Optimize re-use to secure cost competitive supply
Public
29

DUV    product portfolio to support all market segments
DUV     Slide 30
29 Sept. 2021
ength    NA, Half pitch 202020212022202320242025
Continue innovationNXT:2000i on advanced NXT:2050i NXT platform for improved NXT:2100i imaging, overlay and productivity NEXT
critical
ArFi    1.35 NA,38 nm2.0 nm | 275wph1.5 nm | 295wph1.3 nm | 295wph
Leveragemid—c itical of NXT:1980Di advanced NXT platform forNXT:1980Ei improved productivity NXT:1980Fi
2.5 nm | 275wph2.5 nm | 295wph2.5 nm | 330wph
XTXT:1460K
ArF    0.93 NA,57Migratenm to advanced 5 nm | 205wph NXTor platform 7.5 nm| 228wph for improved imaging, overlay and productivity
NXT:1470NEXT
NXT4 nm | 300wph
0.93    NA, 80ProductivitynmXT:1060K increases on XT platformXT:1060K + PEP
5 nm | 205wph5 nm | 220wph
KrF     XTXT:860MXT:860N
Productivity 7increasesnm** | 240 on- 250wphXT platform7.5 nm | 260wph
0.80    NA,110 nm
Migrate to advanced NXT platform for performanceNXT:870and productivityNEXT
NXT7.5 nm | 330wph
i-line    0.65 NA,220ProductivitynmXT:400L increases on XT platform and migrate to next systemXT:400M for high volume applications NEXT
20 nm** | 230wph20 nm** | 250wph
27%34%30%
66%70%
Public
30

EUV 0.33 NA adoption enabled by platform maturity in    
EUV    high-volume manufacturing Slide 31
29 Sept. 2021
100%
3000    System output
Max wafers per day (single system, weekly average) 95%
2500     90%
Installed base system availability
day    4 weeks moving average (end of period) 85%
2000    
per     80%
1500     75% Availability
Wafers     70%
1000     65%
60%
500    
55%
0     50%
2017    2018 201920202021
ASML commitment is expected to bring EUV availability >95%    
and increase wafer per day output >50% by 2025
Source : ASML installed base data     Public
31

EUV: strategic directions    
EUV Enabling cost-efficient scaling for advanced nodes    Slide 32
29 Sept. 2021
Customer value using EUV    ASML EUV product improvements
Better device performance: simpler    • Technology roadmap: per node (resolution), improve
design and superior electrical    imaging, overlay and defectivity (reticle and wafer
Nanometers    performance level)
Less tools needed to meet fab capacity    
due to higher throughput    • Productivity roadmap over time: increase Productivity
Productivity     to >200wph, Availability to >97%
Patterning cost saving for critical layers vs    Improvement sub system focus:
alternatives (3x ArFi immersion and    
above)    
Good wafers     • Source (in-line refill, higher power, high reflective mirror)
per day per cost    Higher yield due to less multiple • Mirrors (mirror heating measure, cooled mirrors)
patterning layers (up to 9%)    
• Stages and reticle (Reticle heating, high-accurate fast
stages, pellicle durability)
Reduced process complexity leading to    • Alignment (# marks, mark size, wafer clamp robustness)
Cycle time and    shorter learning cycles and faster time-to-
time to market    yield
Public
32

High-NA to prevent cycle time and process complexity increase
EUV    like low NA did for immersion Slide 33
29 Sept. 2021
5     Insertionpreferred
EUVEUV
NANA
3     --
u. )     0.330.55
(a. dependent)     DUVEUV- 0.33NAEUV- 0.55NA
complexity cycletime (product    3
0.33-NA insertion supports singleHigh-NA insertion opportunities to
process steps,     patterning to reduce cycle timecontinue Moore’s Law without any
mask     penalty of cycle time increase
2    
AlternativeAlternative
Proposed baselineProposed baseline
1    
10     1001,000
16nm    10nm 7nm5nm3nm2nm
Transistor density [MTr/mm²] Nodes (equivelant node names) [nm]
Note: Assuming 1.2 days per mask layer     Public
33

High-NA EUV: strategic directions    
EUV Enabling cost-efficient scaling for next generation advanced nodes    Slide 34
29 Sept. 2021
Customer value High-NA EUV    ASML High-NA EUV product improvements
0.55 NA enables 1.7x smaller features    
and 2.9x increased density    • Technology roadmap: per node (resolution), improve
Nanometers     imaging, overlay and defectivity (reticle and wafer
level)
Higher imaging contrast enables 40%    
improvement in local CDU    • Productivity roadmap over time: increase Productivity
Performance    1.4x reduced pattern variability at 1.4x
lower dose    
15% Patterning cost saving for critical    Focus for a successful insertion at
layers vs alternatives (2x EUV)    our customers
Good wafers     •Commonality with existing EUV platform to reduce
per day per cost    Higher yield due to less multiple technological risk, cost of development and switch cost
patterning layers: 35% less mask count     at customer
below 2 nm process node    
• Focus on system maturity and serviceability to support
Reduced process complexity leading to     our customer high volume performance expectation
Cycle time and    15% shorter learning cycles and faster •Early engagement with our customers to address
time to market    time-to-yield ecosystems readiness
Public
34

High-NA EUV is in the realization    phase
EUV On multiple ASML and supplier locations     Slide 35
29 Sept. 2021
Oberkochen, Germany optics system manufacturing facilities    
Veldhoven,
the Netherlands,
system bottom test
EUV 0.55 NA optics    
Toulon, France, Frame milling     Wilton, USA,system top test
Public
35

EUV 0.55 NA is expected to be added to EUV portfolio    
EUV    for high volume in 2025—2026 while continue improving the 0.33 NA platformSlide 36
29 Sept. 2021
2020    2021 202220232024³2025
0.33NA continuous imaging,NXE:3600Doverlay and productivity improvementsNXE:3800E in line     NXE:4000F
with customers advanced1.1 nmnode| 160HVMwph requirements.    <1.1 nm | >195 wph / 220wph <0.8nm|>220wph
EUV     ASMLR&DHVM
0.55NA    enabling affordable scaling beyond current decade
EXE:5000EXE:5000 EXE:5200
at ASML fab<1.1 nm | 150 wph <0.8 nm | 220 wph
EXE platform, EUV 0.55 NA     NXE platform, EUV 0.33 NA
Public
36

ST    Commonality across EUV, DUV & High-NA platforms
Slide 37
TRU    Allows faster and more cost-effective innovation, production and maintenance 29 Sept. 2021
DUV     EUV
Alignment Sensor
Common Technology    Level sensor
used in both    Metrology
DUV & EUV platform    Wafer handling
NXT (193 nm dry)
Common Technology    
used in    
DUV products: NXT    
NXT:870    NXT:1470 NXT:2050i
EUV     EUV High-NA
Alignment Sensor Source
Level sensor Metrology
Common Technology    Wafer stager
used in both    Reticle stager
EUV platforms    Wafer handling
37

ST    Maximizing customers’ good wafers per day
Slide 38
TRU    Next to minimizing system down time 29 Sept. 2021
100% 100%100%
System downtime     System downtime serving
according to     customer needs
standardized    
definition    >97% Process-specific inefficiencies
e.g., system down to meet
customer specs, layer
qualification after system down,
defectivity monitoring and more > 90-95%
> 85-90%
System uptime     System uptime producing
capable of producing     customer wafers
wafers    
Historical service model:    New service model:
Maximize scanner availability    Maximize good wafers per day
Public
38

ST    EUV is the most energy efficient solution
Slide 39
TRU    We expect net energy savings of more than 45% over alternative processes 29 Sept. 2021
EUV 0.33EUV 0.55
Electrical power reduction     Electrical power reduction
Immersion to EUV 0.33 productivity [wph]     EUV 0.33 to EUV 0.55 at 220 wph
Side wall Assisted     DryEtch
Quadrupole Patterning     ArFi
EUVLito-Etch-Litho-Etch 0.33 NA - 46%
100 wph     - 45%Metallization
MetrologyLitho-Etch 0.55 NA
145 wph     Deposition
(today)     05101520
WetEtch
220 wph    
(2025)    
0    5 101520
Source: Sri Samavedam a.o., IMEC, “Future of logic scaling: Towards atomic channels and deconstructed chips”, IEDM, Dec 2020, extended by ASML.     Public
39

Technology strategy    
Holistic Lithography roadmap is driven by our unique
Key messages     patterning control solutions that deliver customer value viaSlide 40
29 Sept. 2021
improved on product performance.
• Moore’s Law is alive and well! Industry innovation    • ASML’s comprehensive product portfolio is aligned to our
continues, fueled by system scaling, delivering highly valued     customers’ roadmaps, delivering cost effective solutions in support
semiconductor products.     of all applications from leading edge to mature nodes
• Semiconductor system scaling enables exponential    • Our next generation EUV technology, High-NA, is progressing
performance improvement and energy reduction in support of     well and will be the engine to drive the lithography roadmap into
significant growth of data exchange.     the next decade
• Customers’ roadmaps require continued shrink and    • Continued execution of our strategic priorities is expected to
reduction in edge placement error to drive affordable scaling     provide cost effective solutions for our customers, enable the
into next decade.     extension of the industry roadmap into the next decade, and
support our long-term sustainability commitment
40

Forward Looking Statements    
Slide 41
29 Sept. 2021
This presentation contains statements that are forward-looking, including statements with respect to expected industry and business environment trends including     expected growth, outlook and expected financial results, including expected net sales, gross margin, R&D costs, SG&A costs and effective tax rate, annual revenue     opportunity for 2025, financial model for 2025 and assumptions and expected growth rates and drivers, expected growth including growth rates 2020-2025 and 2020-     2030, total addressable market, growth opportunities beyond 2025 and expected annual growth rate in lithography and metrology and inspection systems and expected     annual growth rate in installed base management, expected trends in addressable market up to 2030, expected trends in Logic and Memory revenue opportunities, long     term growth opportunities and outlook, expected trends in demand and demand drivers, expected benefits and performance of systems and applications, semiconductor     end market trends, expected growth in the semiconductor industry including expected demand growth and capital spend in coming years, expected wafer demand     growth and investments in wafer capacity, expected lithography market demand and growth and spend, growth opportunities and drivers, expected trends in EUV and     DUV demand, sales, outlook, roadmaps, opportunities and capacity growth and expected EUV adoption, profitability, availability, productivity and output and estimated     wafer demand and improvement in value, expected trends in the applications business, expected trends in installed base management including expected revenues     and target margins, expected trends and growth opportunity in the applications business, expectations with respect to high-NA, the expectation of increased output     capacity, plans, strategies and strategic priorities and direction, expectation to increase capacity, output and production to meet demand, the expectation that Moore’s     law will continue and Moore’s law evolution, product, technology and customer roadmaps, and statements and intentions with respect to capital allocation policy,     dividends and share buybacks, including the intention to continue to return significant amounts of cash to shareholders through a combination of share buybacks and     growing annualized dividends and statements with respect to ESG commitment, sustainability strategy, targets, initiatives and milestones. You can generally identify     these statements by the use of words like “may”, “will”, “could”, “should”, “project”, “believe”, “anticipate”, “expect”, “plan”, “estimate”, “forecast”, “potential”, “intend”,     “continue”, “target”, “future”, “progress”, “goal” and variations of these words or comparable words. These statements are not historical facts, but rather are based on     current expectations, estimates, assumptions and projections about our business and our future financial results and readers should not place undue reliance on them.     Forward-looking statements do not guarantee future performance and involve a number of substantial known and unknown risks and uncertainties. These risks and     uncertainties include, without limitation, economic conditions; product demand and semiconductor equipment industry capacity, worldwide demand and manufacturing     capacity utilization for semiconductors, semiconductor end-market trends, the impact of general economic conditions on consumer confidence and demand for our     customers’ products, performance of our systems, the impact of the COVID-19 outbreak and measures taken to contain it on the global economy and financial markets,     as well as on ASML and its customers and suppliers, and other factors that may impact ASML’s sales and gross margin, including customer demand and ASML’s ability     to obtain supplies for its products, the success of R&D programs and technology advances and the pace of new product development and customer acceptance of and     demand for new products, production capacity and our ability to increase capacity to meet demand, the number and timing of systems ordered, shipped and recognized     in revenue, and the risk of order cancellation or push out, production capacity for our systems including the risk of delays in system production and supply chain     capacity, constraints, shortages and disruptions, trends in the semi-conductor industry, our ability to enforce patents and protect intellectual property rights and the     outcome of intellectual property disputes and litigation, availability of raw materials, critical manufacturing equipment and qualified employees and trends in labor     markets, geopolitical factors, trade environment; import/export and national security regulations and orders and their impact on us, ability to meet sustainability targets,     changes in exchange and tax rates, available liquidity and liquidity requirements, our ability to refinance our indebtedness, available cash and distributable reserves for,     and other factors impacting, dividend payments and share repurchases, results of the share repurchase programs and other risks indicated in the risk factors included in     ASML’s Annual Report on Form 20-F for the year ended December 31, 2020 and other filings with and submissions to the US Securities and Exchange Commission.     These forward-looking statements are made only as of the date of this document. We undertake no obligation to update any forward-looking statements after the date of     this report or to conform such statements to actual results or revised expectations, except as required by law.     Public
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ASML SMALL TALK 2021 42