Exhibit 99.3

Public Industry Roadmap and Technology Strategy Martin van den Brink President and Chief Technology Officer

Overview Public Slide 2 8 November 2018 • Moore’s law innovation continues, driven by multiple engines of performance Industry scaling which is expected to accelerate over the next decade Innovation • Continued process technology innovation attracts new applications and increases wafer volume • Customers’ roadmaps require lithography enabled shrink beyond next decade Customers’ Roadmap • Higher wafer volumes at leading edge nodes drive a continued demand for higher productivity, lower cost and simpler processes • Our product portfolio is aligned to industry trends and customer requirements ASML’s Holistic with a detailed product roadmap Litho Solutions • Execution of our strategic priorities will provide required solutions for our Roadmaps customers, enabling cost effective shrink beyond the next decade

Major trends in semiconductor-enabled computing Public Slide 3 8 November 2018 SoC Applications CPU NPU Digital GPU Signal Processor Moore’ Moore’s Law Fast Performanc Performance data Algorithms Cost Cost Data Memory & Storage Source: Sumit Sadana, Micron, Micron Investor Day, May 2018

Public Slide 4 8 November 2018 LPDDR4 A10 Circuit die die packag Dimensional scaling e LPDDR4 Scaling 3D, System- LPDDR4 Patterning and on-chip and die LPDDR4 die circuity shrink advanced packaging Architecture DSP/ Samsung: gate-all- NPU scaling around post 7 nm! Solution optimization Source: Intel, TechInsights, GlobalFoundries, Samsung

Chipmakers accelerate performance for the next decade¹ Process technology innovation accounts for 30% on par with Moore’s prediction2 Public Slide 5 8 November 2018 Improvement opportunities for the next decade 100% >2X 3D stacking /2.4 years 80% Multi-chip architecture Memory integration ormance/Watt 60% Software Perf 2X Micro-architecture Includes 40% System /2.4 years Power management litho Scale 20% Log Process Technology 0 2008 2018 2028 ¹Lisa Su, AMD, “Immersive era in consumer computing”, IEDM, dec 2017 ²Gordon Moore, “Progress in digital integrated Electronics” International; Electronic Device Meeting,, IEEE, 1975, p p 11-13

Customers’ roadmaps show continued need to shrink ASML’s roadmap aligned to deliver solutions Public Slide 6 8 November 2018 DRAM Logic CAGR CAGR High: 10% High: 28% Low: 5% Low: 10%

Innovation attracts new applications Starting at trailing nodes and migrating fast to leading edge Public Slide 7 8 November 2018 7nm 100.0 10nm [M/mm^2] 20nm 28nm Density 10.0 Google TPU 45nm Breeding Transistor iPhone Ax BitMain ASIC Ground 1.0 2009 2011 2013 2015 2017 2019 2021 Year of Introduction Source: Company product announcements

Combined EUV, High NA, DUV and holistic solutions needed to support shrink in the next decade Public Slide 8 8 November 2018 Minimum resolution continues to shrink … … and Logic takes over from DRAM in overlay scaling 100 MPU Mix&match Applications ArFi lithography Foundry On Product Overlay [nm] Single Expose DRAM 3,5 7nm NXT:1980i YieldStar 3D-NAND NXE:3400B Software m ] SE Limit of ArFi [n 3,0 n    o NXT:2000i YieldStar ti 2,5 5nm u NXE:3400C    Software l 2,0 3nm ArFi Next YieldStar eso DRAM NXE:3400C Software r EUV Single 2nm ArFi Next YieldStar ed Expose 1,5 NXE Next Software i r ArFi Multi-patterning 1,0 Logic equ SE Limit of EUV R EUV HiNA Single Multi- Expose 0,5 Patterning Customers request SE Limit of High NA 0,0 complementary product 10 2015 2020 2025 2030 innovation 2005 2010 2015 2020 2025 2030 Year of HVM Source: ASML analysis

Customers’ scaling roadmaps continue Public EUV Production High NA Production Slide 9 Insertion Window Insertion Window 8 November 2018 2017 2018 2019 2020 2021 2022 2023 2024 2025 Node name Logic Logic 10nm 7nm 5nm 3nm 2nm Node name Performance Memory DRAM 1X 1Y 1Z 1 1A 1B Storage Min. ¹⁄₂ pitch /x number of layers Class 2X/x2 2X/x4 1Y/x4 1Y/x8 next Memory Storage Memory Planar 14-15 Today’s status Production1 x number of layers 3D- Development1 NAND x64 x96 x128 x152/x192 x256 >300 Research1 Roadmap2 Source: 1 Customers public statements, IC Knowledge LLC; 2 ASML extrapolations

Our strategy to enable shrink Public Slide 10 8 November 2018 • Strengthen Litho+ leadership with in device metrology enabling correction of Holistic Litho process induced overlay extension • Build a winning position in Pattern Fidelity Control leveraging e-beam metrology and inspection combined with superior computational Litho and fast stages • Drive DUV performance DUV—Continue to lead in innovation performance—Drive operational cost down and improve up-time—Expand installed base business EUV • Deliver on high volume manufacturing, service and financial performance industrialization • Enhance EUV value for future nodes by extending NA 0.33 product portfolio down to the 3nm Logic node • Enable High NA EUV at 3nm Logic node, followed by memory nodes at High NA comparable density

ASML’s Holistic Lithography roadmap optimize patterning performance through patterning, metrology and computational integration Public Slide 11 8 November 2018 Other patterning tools with advanced capability verlay and focus) resist and Process Window process Control EPE Window Optical and E-beam li Detection metrology

Main factors for continued shrink Edge placement error and shrinking litho critical dimension Public Slide 12 8 November 2018 Edge placement error (EPE) and litho critical …and shrink requires ever tighter dimension (CD) main patterning parameters… requirements node x node x+2 Intended cut X Smaller litho CD uniformity Litho critical dimension error Overlay critical needed dimension error Better EPE Edge placement error performance (EPE): combined error needed (overlay of overlay and CD and CD control) uniformity

Applications Product Roadmap 2017 2018 2019 2020 2021 2022 1 Pattern Fidelity Control Litho InSight Litho Overlay & Focus control Control Edge Placement Control Yield Aware Control erface ol Matching BMMO2 Layout independent matching XOPO EUV-DUV on product matching Next Increase adjustable Int Contr In-device metrology scanner knobs, driving    Overlay Ov WLC OVO3 extensions for high order intra field correction Next denser adjustments and enabling dense on Scanner Focus / Dose product metrology se exposure control IMO 3 extension for higher order corrections Overlay/Focus YS tinuous wavelength source YieldStar 380 Dual Wavelength meas High throughput Optical In-Die Overlay 1375 5mm targets Next Large field high resolution e-beam Develop pattern Through Stack NanoScan 3100 18.5 Next >18. Aggressive multi-wavelength Metrology fidelity and defect metrology & control (robustness) and productivity Device CD eP5 1nm resolution, 12mm x 12mm field of view, 0.1nm p Next Enhanced YieldStar roadmap Pattern Fidelity ePfm5 1nm resolution, 10nm defect size, ADI, AEI, LELE Next Enhanced Process 2 eScan 430 3nm pixel size with enhanced inspection s Aggressive OPC beam eScan 420 ³5nm pixel, 90mm /hr @ 10nm ction E—Monitoring roadmap supporting Multi-beam metrology systems Multi-beam 9 beams Next >9 EPE requirements Inspe in realization, extensions under using machine Yield study built on 3 competence /hr @ 2nm learning enables by Engineering pillars: e-beam, fast stage and computational technology Multi-beam >100 b fast SEM’s OPC Model Accuracy 1.5nm 1.2nm 1 Timing and functionality for NXT interfaces, NXE timing & functionality differ; BMMO: Baseliner Matched Machine Overlay; WLC: Wafer Level Control; MAM: Move-Acquire-Measure, OPC: Optical Proximity Correction, 2D CD accuracy 3s

Better accuracy of lithography models by deep learning Enabled by fast e-beam metrology and physical based models Public Slide 14 8 November 2018 Example 1 Data-driven training based on fitting ASML Deep spec and wafer measurements learning model Accuracy Large volume wafer metrology data, further enhanced by fast e-beam Captures complex effects Physical driven training using required by the data Example 2 physics based lithography models Feature extraction: Final resist model trained does not contain human- Stability Physical Resist Data expansion engineered model Resist surface through simulated terms and achieves Shrinkage tress contours better accuracy

Yield Star In-Device Metrology improves electrical yield Compared to SEM on word line DRAM layer Public Slide 15 8 November 2018 Wafers/Lots Wafer/Lots Controlled with Controlled with YieldStar IDM High Voltage SEM Electrical Resistance Test—B A-B = 0  Zero Overlay A    DRAM Memory Cell Electrical Active Resistance A + B Word Lines    IDM measured Overlay fingerprint 2.3nm fingerprint after after IDM Control 4.9nm SEM Control

Applications: expanding solution space Drives growing product portfolio Public Slide 16 8 November 2018 Computational E-Beam Metrology Optical Metrology Process Control Lithography & Inspection • Deep learning and fast • Entering growing after- • Expanding CD-SEM • Process control e-beam metrology etch in device overlay opportunity solution running in (HMI) differentiate our market with YS:1375 volume production • Process Window model accuracy • Opening new use- Qualification • Focus on process • Better accuracy cases with machine opportunity for e-beam control market enables wafer defect learning, instead of inspection dynamics aligned to prediction, enabling reconstruction value of yield-based • Progressing high higher speed control productivity multi-inspection beam roadmap

DUV Product Roadmap Extending throughput for cost reduction and overlay for yield improvement Public Slide 17 8 November 2018 Key immersion innovations in alignment, wafer table and level sensor synced with NXE for tighter overlay matching 2017 2018 2021 2022 …. 2025 ArFi NXT:1980i NXT t 1.35 NA 1.5nm| 285wph 2.5nm | 275wph 2.0nm | 275wph 38nm ArF XT:1460K +BOOST ArF common plat 0.93 NA 220wph 3nm| >250w 5nm | 205wph 57nm New fast stages in common KrF XT:1060K NXT dry-immersion platform    0.93 NA NEXT 5nm | 205wph in development for better 80nm KrF Next productvity and accuracy 0.80 NA XT:860M +Throughput package 120nm 7nm | 240wph 250wph i-line XT:400L +Overlay package Continuous cost, quality and 0.65 NA productivity improvements 20nm | 230wph 15nm | 230wph 350nm over all products Product Released Current Development XT enhancements to address Matched Machine Product status Overlay|Throughput Definition 3D NAND requirements

NXT:2000i performance exceeding expectations As measured on multiple systems shipped Public Slide 18 8 November 2018 Alignment sensor    Additional features • More process robustness • Improved grid setup for better • Higher yield overlay and calibration • Improved projection lens modeling and heating control • Better wafer heating control Level sensor Wafer Table • Reduced process • Improved matching to EUV dependency • Improved flatness & endurance DCO: Dedicated Chuck Overlay • Improved matching MMO: Matched Machine Overlay

DUV: mix and match with EUV and drive to perfection Public Slide 19 8 November 2018 Innovation Leadership Cost & uptime Installed Base Management • Leadership in Immersion with the NXT:2000i • NXT installed base has demonstrated • Multiple opportunities to generate service featuring a next generation alignment >97% availability revenue over the lifetime of a system sensor, focus & levelling system and laser • • NXT:2000i already demonstrated 95% Extended immersion upgrade path to innovation availability and ramped to mature reliability NXT:2000i performance levels • We plan to further extend our leadership with levels in 15 weeks, 2/3 the time required for • Strengthened our Installed Base continued innovation in wafer stage and lens the previous system NXT:1980i Management product portfolio with value technology, also enabling extensions in our • Leverage commonalities between models based service products Application product portfolio and platforms for cost efficiency and de- • Implementation of NXT platform for ArF risking production together with the next generation stages Next generation stage NXT:2000i reliability ramp-up Extendibility upgrade paths

EUV: deliver performance for volume manufacturing and extend roadmap for continued cost effective shrink Public Slide 20 8 November 2018 3400B uptime improving to >90% Extension to 3 nm node, through Acceleration improvements to for 2018/ 2019 HVM: Modular EXE5000 common subsystems, <1.5nm overlay and 170wph vessel acceleration to <1nm overlay and >185wph EUV NXE ay NXE 0.33 NA 2.5 | 125wph 2.0nm | 125wph 1.5nm 155 1.5nm | 170wph 1.1nm | ³ 185wph 13nm 0.55 NA High NA 8nm Product High NA platform reducing need for Matched Machine Overlay|Throughput multi-patterning 0.33 NA enabling long term litho simplification NXE:3400 EXE:5000 1 Tput: Throughput upgrade (wph)

NXE:3400 Matched Machine Overlay Public Performance well below NXE:3350 and specifications Slide 21 8 November 2018 2.5 Average NXE:3350 Spec [nm] 2.0 Overlay 1.5 Machine 1.0 Matched 0.5 0.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 systems

Driving commonality between High NA and 0.33 NA Reduces risk, lowers cost and allow 0.33 extension Public Slide 22 8 November 2018 Illuminator Projection Mirror ‘rework’ Source Reticle Masking Unicom Reticle Stage Reticle Handler Optics Optics process at Zeiss Specific Common Mechanical Broad band Electronics & SW Cooling Hood Image sensor Wafer Stage Alignment sensor Wafer Handler architecture Level Sensor architectures

Larger NA results in higher effective throughput1 2 Public Less number of Litho Etch steps and transmission improvement Slide 23 8 November 2018 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 2 1 2 2 2 3 3 3 1 2 1 1 1 2 3 2 3 2 2 1 1 1 1 2 2 3 1 3 1 3 1 Effective throughput = throughput / # LE steps Quasar 2 Illumination LE: Litho Etch

EUV: two accelerated development programs in parallel after having achieved volume production feasibility metrics Public Slide 24 8 November 2018 0.33 NA Summary High NA summary • ASML and supply chain preparing for planned • System design completed, module design progressing and key production ramping suppliers selected. • Dedicated focus to improve availability across sites • Customers’ roadmap aligned with the High NA introduction plan and systems starting at 3nm. • Accelerated roadmap of NXE:3400C in order to deliver • Three customers have committed to 4 R&D systems and higher productivity tool, >170wph with improved 8 options for early volume systems. Results in total up to availability 1.5 B€ Customer commitments • Roadmap extended to the 3nm node working mix • Design of metrology system by joint ASML-Zeiss team and and match with DUV and High NA using common manufacturing of optics started. High NA and 0.33 NA innovations • Extended collaboration with imec in support of necessary developments in ecosystem and demo access for customers

Summary Public Slide 25 8 November 2018 • Moore’s law innovation continues, driven by multiple engines of performance Industry scaling which is expected to accelerate over the next decade Innovation • Continued process technology innovation attracts new applications and increases wafer volume • Customers’ roadmaps require lithography enabled shrink beyond next decade Customers’ Roadmap • Higher wafer volumes at leading edge nodes drive a continued demand for higher productivity, lower cost and simpler processes • Our product portfolio is aligned to industry trends and customer requirements ASML’s Holistic with a detailed product roadmap Litho Solutions • Execution of our strategic priorities will provide required solutions for our Roadmaps customers, enabling cost effective shrink beyond the next decade

Forward Looking Statements Public Slide 26 This document contains statements relating to certain projections, business trends and other matters that are forward-looking, including statements with respect to expected trends and outlook, 8 November 2018 strategy, bookings, expected financial results and trends, including expected sales, EUV revenue, gross margin, capital expenditures, R&D and SG&A expenses, cash conversion cycle, and target effective annualized tax rate, and expected financial results and trends for the rest of 2018 and 2019, expected revenue growth and demand for ASML’s products in logic and memory, expected annual revenue opportunity in 2020 and for 2025 and expected EPS potential in 2020 with significant growth in 2025, expected trends in the lithography system market, fab capacity by segment, the automotive and artificial intelligence industries, connectivity, semiconductor end markets and new semiconductor nodes, expected acceleration of chipmakers’ performance for the next decade, expected EUV insertion and transistor density growth, trends in DUV systems revenue and Holistic Lithography and installed based management revenues, statements with respect to expectations regarding future DUV sales, including composition, margins, improvement of operations and performance, DUV product roadmaps, expected benefits of the holistic productivity approach, including in terms of wafers per year, expected industry trends and expected trends in the business environment, statements with respect to customer demand and the commitment of customers to High NA machines and to insert EUV into volume manufacturing by ordering systems, expected future operation of the High NA joint lab, statements with respect to holistic lithography roadmaps and roadmap acceleration, including the introduction of higher productivity systems in 2019 (including the expected shipment of NXE:3400C and expected timing thereof) and the expected benefits, ASML’s commitment to volume manufacturing and related expected plans until 2030, ASML’s commitment to secure system performance, shipments, and support for volume manufacturing, including availability, timing of and progress supporting EUV ramp and improving consistency, productivity, throughput, and production and service capability enabling required volume as planned, including expected shipments, statements with respect to growth of fab capacity driving demand in lithography systems, planned customer fabs for 200 systems and expected first output in 2019, expected EUV value increase and increase in EUV margins and ASML’s expectation of EUV profitability at the DUV level, expected installed base of EUV systems, expected customer buildout of capacity for EUV systems, EUV estimated demand by market, expected increase in lithography intensity, statements with respect to the expected benefits of EUV, including year-on-year cost reduction and system performance, and of the introduction of the new DUV system and expected demand for such system, the expected benefits of HMI’s e-beam metrology capabilities, including the expansion of ASML’s integrated Holistic Lithography solutions through the introduction of a new class of pattern fidelity control, the extension of EUV to enable cost effective single patterning shrink with EUV, statements with respect to ASML’s applications business, including statements with respect to expected results in 2018, expected growth of the applications business and expected drivers of growth, expected growth in margins, continued shrink and drivers, and expected accuracy, defect control and performance improvements, shrink being a key driver supporting innovation and providing long-term industry growth, lithography enabling affordable shrink and delivering value to customers, DUV, Holistic Lithography and EUV providing unique value drivers for ASML and its customers, expected industry innovation, the expected continuation of Moore’s law and that EUV will continue to enable Moore’s law and drive long term value for ASML beyond the next decade, intention to return excess cash to shareholders through stable or growing dividends and regularly timed share buybacks in line with ASML’s policy, statements with respect to the expectation to continue to return cash to shareholders through dividends and share buybacks, and statements with respect to the expected impact of accounting standards. You can generally identify these statements by the use of words like “may”, “will”, “could”, “should”, “project”, “believe”, “anticipate”, “expect”, “plan”, “estimate”, “forecast”, “potential”, “intend”, “continue”, “targets”, “commits to secure” and variations of these words or comparable words. These statements are not historical facts, but rather are based on current expectations, estimates, assumptions and projections about the business and our future financial results and readers should not place undue reliance on them. Forward-looking statements do not guarantee future performance and involve risks and uncertainties. These risks and uncertainties include, without limitation, economic conditions, product demand and semiconductor equipment industry capacity, worldwide demand and manufacturing capacity utilization for semiconductors, including the impact of general economic conditions on consumer confidence and demand for our customers’ products, competitive products and pricing, the impact of any manufacturing efficiencies and capacity constraints, performance of our systems, the continuing success of technology advances and the related pace of new product development and customer acceptance of and demand for new products including EUV and DUV, the number and timing of EUV and DUV systems shipped and recognized in revenue, timing of EUV orders and the risk of order cancellation or push out, EUV production capacity, delays in EUV systems production and development and volume production by customers, including meeting development requirements for volume production, demand for EUV systems being sufficient to result in utilization of EUV facilities in which ASML has made significant investments, potential inability to successfully integrate acquired businesses to create value for our customers, our ability to enforce patents and protect intellectual property rights, the outcome of intellectual property litigation, availability of raw materials, critical manufacturing equipment and qualified employees, trade environment, changes in exchange rates, changes in tax rates, available cash and liquidity, our ability to refinance our indebtedness, distributable reserves for dividend payments and share repurchases, results of the share repurchase plan and other risks indicated in the risk factors included in ASML’s Annual Report on Form 20-F and other filings with the US Securities and Exchange Commission. These forward-looking statements are made only as of the date of this document. We do not undertake to update or revise the forward-looking statements, whether as a result of new information, future events or otherwise.

Public INVESTOR DAY ASML SMALLTALK 2018 VELDHOVENE