EX-99.5

EX-99.5 6 u56855exv99w5.htm EX-99.5 EX-99.5

Exhibit 99.5

ASML, Brion and Computational Lithography Neal Callan 15 October 2008, Veldhoven

'02 '03 '04 '05 '06 '07 '08 '09 '10 '11 '12 '13 '14 Year of production start* Resolution, "Shrink" (nm) 100 80 60 40 30 20 50 *Process development 1.5 ~ 2 years in advance (updated 5/08) 200 Chip makers want shrink to continue (based on the average of multiple customers' input) today DRAM Logic NAND Flash

Challenge: image 22 nm features with 193 nm light waves Creating thin lines with a broad brush

Today '02 '03 '04 '05 '06 '07 '08 '09 '10 '11 '12 '13 '14 Year of production start* Resolution, "Shrink" (nm) 100 80 60 40 30 20 50 *Process development 1.5 ~ 2 years in advance (updated 5/08) 200 With Double Patterning shrink continues But ... help is needed from Brion software and ASML scanner know-how Brion and ASML DPT solutions DRAM Logic NAND Flash

Contents Computational Lithography today Brion and Holistic Lithography Combine mask and shape of light source = Source-Mask Optimization (SMO) Improved mask designs -- Open standards for mask design The need to match scanners

Computational Lithography starts here Lithography RET/OPC, Litho Verification, Mask Proximity Correction Scanner-to-pattern tuning Metrology Model predictive controller DoseMapper & GridMapper Printed wafers Measured CD & overlay Computational Litho Wafer Litho Mask making Dose & Grid corrections Scanner settings Source Mask Optimization Brion Litho Exploration Device pattern Device pattern Brion Mask Design Illumination setting

Combine mask and shape of light source (SMO) Optimizing source and mask complexity for best imaging Standard Customized Customized Unconstrained Unconstrained Standard Multi-pole Multi-ring Next Generation Pixelated method OPC with Modelbased Scattering Bars New Mask Optimization Unconstrained (pixelated) OPC 22 nm possible 22 nm possible 22 nm possible Manu- facturing constrained Manu- facturing constrained Manu- facturing constrained Increased DOE complexity Increased performance Increased Mask complexity Optimal manufacturing solution Increased performance NOW Q1 2009 Q1 2009 NOW Q1 2009

Open standards for the industry Broad proliferation of ASML scanner info/models possible Through Brion, ASML will proliferate ASML scanner models throughout the DFM value chain via the Virtual Scanner Pack (VSP) Customers who use design or comp litho tools from anyone can access ASML scanner models through the VSP Good for chip design software companies Good for chip manufacturers Available end Q4 2008 Litho ~$5B ASML Canon Nikon Verification ~$40M Synopsys Mentor Graphics ASML Brion Design $1.5B Synopsys Mentor Graphics Cadence Magma, others OPC ~$80M Synopsys Mentor Graphics ASML Brion Cadence

Optical Proximity Correction (OPC) OPC is required for advanced masks to ensure printability This is the pattern that needs to appear on the wafer without Brion software software software software software software software software Pattern design after Brion software Note the changes that accentuate the pattern added by Brion software Due to light scattering at these nanoscopic levels, the image blurs The light scattering is compensated and the image is good image is good image is good image is good image is good image is good Light MASK Lithography Process Light MASK

Litho double patterning solutions (DPT) Brion's Litho DPT provides crucial solutions such as Gate-aware splitting Balanced splitting for dense layers Balanced splitting for sparse layers

Computational lithography needs accurate modeling ASML scanner knowledge enables better image prediction ASML scanner knowledge improves modeling accuracy Accurate modeling enables low k1 RET solutions Source Mask Optimization Double Patterning Double Exposure Model based scattering bars

Computational Lithography shifts to image-based More layers requiring increasingly sophisticated OPC 45 nm 32 nm 22 nm 65 nm Poly Active Metal1 Contact Via1 Metal2 MetalX ViaX Poly Active Metal1 Contact Via1 Metal2 MetalX ViaX Poly Active Metal1 Contact Via1 Metal2 MetalX ViaX Poly Active Metal1 Contact Via1 Metal2 ViaX 0 2 4 6 8 10 12 14 16 Normalized Computational Load MetalX At each node, the number of complex OPC layers increases Brion has the most mature image-based OPC and verification products Computational time/load is increasing dramatically with each successive node A key element of Brion's strategy is to deliver consistent cycle time despite increasing computational load

Lithography in the future: Holistic Lithography requires a combination of Computational and Wafer lithography Lithography Source Mask Optimization RET/OPC, Litho Verification, Mask Proximity Correction Scanner-to-pattern tuning Metrology Model predictive controller DoseMapper & GridMapper Illumination setting Device pattern Printed wafers Measured CD & overlay Computational Litho Wafer Litho Mask making Dose & Grid corrections Scanner settings Brion Plus

Process control requires match scanners Higher productivity with consistent yield Mix of machines Create model of full chip differences between scanners Solution: Measure differences between a few areas in chip per scanner Same imaging better yield Mask (Brion's OPC) Brion software plus ASML know- ledge to adjust knobs on each scanner so that they match

Added complexity to match scanners Simple core structures no longer enough Yesterday -- Simple, core patterns were matched NAND wordline Periphery Today -- All critical patterns need to be simultaneously matched High performance SRAM

In Summary Brion + ASML optimizes the design to the scanners Source-Mask Optimization Double Patterning Virtual Scanner Pack Brion + ASML optimizes the scanners to the designs Holistic Lithography -- matching