-----BEGIN PRIVACY-ENHANCED MESSAGE----- Proc-Type: 2001,MIC-CLEAR Originator-Name: webmaster@www.sec.gov Originator-Key-Asymmetric: MFgwCgYEVQgBAQICAf8DSgAwRwJAW2sNKK9AVtBzYZmr6aGjlWyK3XmZv3dTINen TWSM7vrzLADbmYQaionwg5sDW3P6oaM5D3tdezXMm7z1T+B+twIDAQAB MIC-Info: RSA-MD5,RSA, JNOhk4XT+/IDwaemtCw5S6UdDP/7XILjpGG+MLwoTelpGuGqoYbKXXYkVhvnSCeN 4T8A/rHKjKLcbZ2JmPMxqw== 0001178913-05-000527.txt : 20050413 0001178913-05-000527.hdr.sgml : 20050413 20050413103102 ACCESSION NUMBER: 0001178913-05-000527 CONFORMED SUBMISSION TYPE: 6-K PUBLIC DOCUMENT COUNT: 3 CONFORMED PERIOD OF REPORT: 20050413 FILED AS OF DATE: 20050413 DATE AS OF CHANGE: 20050413 FILER: COMPANY DATA: COMPANY CONFORMED NAME: TOWER SEMICONDUCTOR LTD CENTRAL INDEX KEY: 0000928876 STANDARD INDUSTRIAL CLASSIFICATION: SEMICONDUCTORS & RELATED DEVICES [3674] IRS NUMBER: 000000000 FISCAL YEAR END: 1231 FILING VALUES: FORM TYPE: 6-K SEC ACT: 1934 Act SEC FILE NUMBER: 000-24790 FILM NUMBER: 05747536 BUSINESS ADDRESS: STREET 1: RAMAT GAVRIEL STREET 2: P O BOX 619 CITY: MIGDAL HAEMEK 23105 STATE: L3 BUSINESS PHONE: 97246506611 MAIL ADDRESS: STREET 1: RAMAT GAVRIEL STREET 2: P O BOX 619 CITY: MIGDAL HAEMEK 23105 STATE: L3 ZIP: N-A 6-K 1 zk51469.txt FORM 6-K SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 For the month of April 2005 No.2 TOWER SEMICONDUCTOR LTD. (Translation of registrant's name into English) P.O. BOX 619, MIGDAL HAEMEK, ISRAEL 23105 (Address of principal executive offices) Indicate by check mark whether the registrant files or will file annual reports under cover Form 20-F or Form 40-F. Form 20-F [X] Form 40-F [_] Indicate by check mark whether the registrant by furnishing the information contained in this Form is also thereby furnishing the information to the Commission pursuant to Rule 12g3-2(b) under the Securities Exchange Act of 1934. Yes [_] No [X] On April 13, 2005, the Registrant announced the debut of its in-house 0.18- and 0.13-micron libraries. Attached hereto as Exhibit 99.1 is a copy of the press release. On April 13, 2005, the Registrant announced that Synopsys will distribute Tower Semiconductor's 0.18- and 0.13-micron silicon libraries within DesignWare library. Attached hereto as Exhibit 99.2 is a copy of the press release. This Form 6-K is being incorporated by reference into all effective registration statements filed by us under the Securities Act of 1933. SIGNATURES Pursuant to the requirements of the Securities Exchange Act of 1934, the registrant has duly caused this report to be signed on its behalf by the undersigned, thereunto duly authorized. TOWER SEMICONDUCTOR LTD. Date: April 13, 2005 By: /s/ Nati Somekh Gilboa -------------------------- Nati Somekh Gilboa Corporate Secretary EX-99 2 exhibit_99-1.txt Exhibit 99.1 TOWER SEMICONDUCTOR DEBUTS IN-HOUSE 0.18- AND 0.13-MICRON LIBRARIES Standard Cells, I/Os and Memory Compilers, Based on Synopsys Technology MIGDAL HAEMEK, ISRAEL, April 13, 2005 -- Tower Semiconductor Ltd. (NASDAQ: TSEM; TASE: TSEM), a pure-play independent specialty foundry, today announced the introduction of its in-house set of 0.18 and 0.13-micron design libraries. Tower Semiconductor's standard cells, I/Os and memory compilers, for use in complex system-on-chip (SoC) designs, are based on Synopsys' library technology, and are available to Tower customers at no charge. Tower's 0.13-micron libraries will augment the existing 0.18-micron libraries, which were proven on silicon and have been used in multiple high-volume customer designs. Tower libraries include a comprehensive set of views for leading EDA tools. "In line with our specialized foundry strategy, Tower customers can now enjoy flexible, in-house customization to meet specific customer and technology segment needs," said Rafi Nave, vice president of customer services, Tower Semiconductor. "Our customers can now benefit from high-quality, low-risk solutions, resulting in faster time-to-market and faster time-to-production in the most affordable way." The high-performance, high-density library is handcrafted to Tower Semiconductor's process helping ensure tight compliance with its design rules. The standard cells have been optimized for high place-and-route density. A wide range of I/Os with over-voltage input tolerance, noise-quieting circuitry and ESD protection are available in both in-line and staggered configuration. Memory compilers for ROM, high-density SRAM and dual-port RAM provide high performance, high density and configuration flexibility. Page 4 The addition of Tower's 0.18- and 0.13-micron libraries to other libraries from ARM (formerly Artisan Components) (LSE:ARM; NASDAQ:ARMHY) and Virage Logic (NASDAQ:VIRL) provides Tower customers with a broad choice of IP solutions to meet their unique requirements. For more information about the Tower libraries, visit www.towersemi.com. ABOUT TOWER SEMICONDUCTOR LTD. Tower Semiconductor Ltd. is a pure-play independent specialty foundry established in 1993. The company manufactures integrated circuits with geometries ranging from 1.0 to 0.13 microns; it also provides complementary technical services and design support. In addition to digital CMOS process technology, Tower offers advanced non-volatile memory solutions, mixed-signal and CMOS image-sensor technologies. To provide world-class customer service, the company maintains two manufacturing facilities: Fab 1 has process technologies from 1.0 to 0.35 microns and can produce up to 16,000 150mm wafers per month. Fab 2 offers 0.18-micron and below standard and specialized process technologies, and has a current capacity of up to 15,000 200mm wafers per month. The Tower Web site is located at www.towersemi.com. SAFE HARBOR THIS PRESS RELEASE INCLUDES FORWARD-LOOKING STATEMENTS, WHICH ARE SUBJECT TO RISKS AND UNCERTAINTIES. ACTUAL RESULTS MAY VARY FROM THOSE PROJECTED OR IMPLIED BY SUCH FORWARD-LOOKING STATEMENTS. POTENTIAL RISKS AND UNCERTAINTIES INCLUDE, WITHOUT LIMITATION, RISKS AND UNCERTAINTIES ASSOCIATED WITH: (I) THE SUCCESSFUL COMPLETION OF THE 0.13-MICRON PROCESS TECHNOLOGY TRANSFER (II) MARKET DEMAND FOR 0.18 AND 0.13-MICRON TECHNOLOGY MANUFACTURING SERVICES; (III) FINAL QUALIFICATION OF THE 0.13 MICRON PROCESS (IV) TIMELY AND SUCCESSFUL VALIDATION OF 0.13-MICRON IP OFFERING. A COMPLETE DISCUSSION OF RISKS AND UNCERTAINTIES THAT MAY AFFECT THE ACCURACY OF FORWARD-LOOKING STATEMENTS INCLUDED IN THIS PRESS RELEASE OR WHICH MAY OTHERWISE AFFECT OUR BUSINESS IS INCLUDED UNDER THE HEADING "RISK FACTORS" IN OUR MOST RECENT ANNUAL REPORT ON FORMS 20-F AND 6-K, AS WERE FILED WITH THE SECURITIES AND EXCHANGE COMMISSION AND THE ISRAEL SECURITIES AUTHORITY. CONTACTS: Pacifico Inc. PR Agency Contact Mary Curtis, +1 408 293 8600 mcurtis@pacifico.com Tower Semiconductor USA: Michael Axelrod, +1 408 330 6871 pr@towersemi.com Page 5 EX-99 3 exhibit_99-2.txt Exhibit 99.2 SYNOPSYS TO DISTRIBUTE TOWER SEMICONDUCTOR'S 0.18- AND 0.13-MICRON SILICON LIBRARIES WITHIN DESIGNWARE LIBRARY TOWER'S COMPLETE SET OF STANDARD CELLS, I/OS AND MEMORY COMPILERS AVAILABLE TO MORE THAN 25,000 DESIGNWARE LIBRARY USERS MOUNTAIN VIEW, CALIF. AND MIGDAL HAEMEK, ISRAEL -- APRIL 13, 2005 - Synopsys, Inc. (Nasdaq:SNPS), a world leader in semiconductor design software, and Tower Semiconductor Ltd. (NASDAQ: TSEM; TASE: TSEM), a pure-play independent specialty foundry, today announced that Tower's in-house set of 0.18-micron standard cells, I/Os and memory libraries are now available through Synopsys' DesignWare(R) Library. As a result, more than 25,000 DesignWare Library licensees now have access to Tower Semiconductor's 0.18-micron libraries, at no additional charge, for use in complex system-on-chip (SoC) designs. Starting in the third quarter of this year, licensees are expected to have access to Tower's 0.13-micron libraries. The 0.18-micron libraries include a complete set of views fully validated in silicon in high-volume production, as well as views for third-party EDA tools. The library distribution agreement with Synopsys also includes the future distribution of Tower's 0.13-micron libraries through the DesignWare Library. "We have successfully used the Tower 0.18-micron standard cells and I/Os in our design. The high quality of the library and the expert support staff from Synopsys enabled us to smoothly meet our design goals," said Alan Tsun, vice president of ESP development engineering at QuickLogic (NASDAQ: QUIK). "Including the Tower library in the DesignWare Library means our designers will have easy library access with effective support and regular updates. This greatly simplifies our IP procurement and administrative processes." "Distributing our technology-optimized libraries through the Synopsys DesignWare Library enables us to reach out to a very large number of SoC designers who are targeting our 0.18-micron technologies," said Rafi Nave, vice president of customer services at Tower Semiconductor. "We worked closely with Synopsys to ensure a smooth path to silicon and the support given by Synopsys' experts will help ensure our customers' design success." Page 6 "With this library distribution agreement, Synopsys and Tower are answering designers' requests for a complete RTL-to-GDSII design environment with streamlined access to essential IP," said Guri Stark, vice president of Marketing, Synopsys Solutions Group. "The addition of Tower's foundry libraries to the DesignWare Library IP portfolio provides our mutual customers with an even greater array of choices when they need reliable, proven IP." PRICING AND AVAILABILITY The Tower 0.18-micron standard cells, I/Os and memories are currently available for no additional cost to all current DesignWare Library licensees. Tower's 0.13-micron simulated libraries are expected to be available in the third quarter of this year. Requests to download the Tower libraries can be made at www.synopsys.com/dwrequest. ABOUT DESIGNWARE LIBRARY Synopsys DesignWare IP enables designers to more cost effectively create and verify complex SoCs, ASICs and FPGAs. The broad IP portfolio includes synthesizable implementation IP, hardened PHYs and verification IP. DesignWare IP, combined with Synopsys' robust IP development methodology, extensive investment in quality and comprehensive worldwide technical support, gives designers a faster, more predictable and lower risk path to chip success. The DesignWare Library portfolio includes foundry libraries, verification IP, AMBA(TM) bus IP and peripherals, memories, building block IP and microcontrollers. All are available under one license with no additional costs, per use fees, or royalties. For a complete directory of Synopsys IP visit: www.synopsys.com/ipdirectory ABOUT TOWER SEMICONDUCTOR LTD. Tower Semiconductor Ltd. is a pure-play independent specialty foundry established in 1993. The company manufactures integrated circuits with geometries ranging from 1.0 to 0.13-microns; it also provides complementary technical services and design support. In addition to digital CMOS process technology, Tower offers advanced non-volatile memory solutions, mixed-signal and CMOS image-sensor technologies. To provide world-class customer service, the company maintains two manufacturing facilities: Fab 1 has process technologies from 1.0 to 0.35 microns and can produce up to 16,000 150mm wafers per month. Fab 2 offers 0.18-micron and below standard and specialized process technologies, and has a current capacity of up to 15,000 200mm wafers per month. The Tower Web site is located at www.towersemi.com. Page 7 ABOUT SYNOPSYS Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA) software for integrated circuit (IC) design. The company delivers technology-leading IC design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California, and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/. FORWARD LOOKING STATEMENTS THIS PRESS RELEASE INCLUDES FORWARD-LOOKING STATEMENTS WITHIN THE MEANING OF THE SAFE HARBOR PROVISIONS OF SECTION 21E OF THE SECURITIES EXCHANGE ACT OF 1934, WHICH ARE SUBJECT TO RISKS AND UNCERTAINTIES, INCLUDING STATEMENTS REGARDING (I) THE EXPECTED BENEFITS AND DATES OF AVAILABILITY OF TOWER'S 0.13-MICRON PROCESS TECHNOLOGY TRANSFER, (II) MARKET DEMAND FOR 0.18- AND 0.13-MICRON TECHNOLOGY MANUFACTURING SERVICES, (III) FINAL QUALIFICATION OF THE 0.13 MICRON PROCESS, AND (IV) TIMELY AND SUCCESSFUL VALIDATION OF 0.13-MICRON IP OFFERING. THESE STATEMENTS ARE BASED ON SYNOPSYS' AND TOWER'S CURRENT EXPECTATIONS AND BELIEFS. ACTUAL RESULTS COULD DIFFER MATERIALLY FROM THE RESULTS IMPLIED BY THESE STATEMENTS AS A RESULT OF UNFORESEEN DIFFICULTIES IN FINALIZING THE PRODUCTION RELEASE OF THE 0.13-MICRON TECHNOLOGY, UNCERTAINTIES ATTENDANT TO ANY NEW MANUFACTURING SOLUTION AND THE OTHER FACTORS DESCRIBED IN SYNOPSYS' QUARTERLY REPORT ON FORM 10-Q FOR THE FISCAL QUARTER ENDED JANUARY 31, 2004, IN THE CASE OF SYNOPSYS, AND IN TOWER'S MOST RECENT ANNUAL REPORT ON FORMS 20-F AND 6-K, IN THE CASE OF TOWER, IN EACH CASE AS FILED WITH THE SECURITIES AND EXCHANGE COMMISSION AND THE ISRAEL SECURITIES AUTHORITY, IF APPLICABLE. Page 8 Synopsys and DesignWare are registered trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners. CONTACTS: Synopsys, Inc. Troy Wood, +1 650 584 5717 twood@synopsys.com Edelman Julie Crabill, +1 650 429 2732 julie.crabill@edelman.com Pacifico Inc. PR Agency for Tower Mary Curtis, +1 408 293 8600 mcurtis@pacifico.com Tower Semiconductor USA Michael Axelrod, +1 408 330 6871 pr@towersemi.com Page 9 -----END PRIVACY-ENHANCED MESSAGE-----