UNITED STATES SECURITIES AND EXCHANGE COMMISSION

                         WASHINGTON, D.C. 20549

                                FORM 8-K


                              CURRENT REPORT



                      PURSUANT TO SECTION 13 OR 15(d) OF 
                      THE SECURITIES EXCHANGE ACT OF 1934


Date of Report (Date of earliest event reported):  May 13, 1997



                    NATIONAL SEMICONDUCTOR CORPORATION 
                    ----------------------------------
          (Exact name of registrant as specified in its charter)


        DELAWARE              1-6453                   95-2095071
        --------              ------                   ----------
(State of incorporation)    (Commission             (I.R.S. Employer
                             File Number)            Identification No.)



                 2900 Semiconductor Drive, P.O. Box 58090
                   Santa Clara, California  95052-8090
                   -----------------------------------
                 (Address of principal executive offices)


Registrant's telephone number, including area code:  (408) 721-5000





NATIONAL SEMICONDUCTOR CORPORATION

INDEX



                                                          Page No.
                                                          --------

Item 5. Other Events                                         3

Item 7. Financial Statements and Exhibits                    5

Signature                                                    6





Item 5. Other Events
- -------------------

In June 1996, under the leadership of a new Chief Executive Officer, 
National Semiconductor Corporation ("the Company") adopted a strategy to 
focus upon and leverage its strength in traditionally high margin analog 
and mixed signal products.  As part of the strategy to concentrate on 
these product areas, the Company decided to divest its Logic, Memory and 
Discrete product divisions which were more mature businesses with slower 
growth rates and generally lower margins than the Analog and Mixed 
Signal product divisions.  These divisions were grouped under the 
Fairchild Semiconductor name and subsequently divested on March 11, 
1997.  The impact of the Fairchild divestiture on the fourth quarter 
results of operations is described in the Company's press release dated 
May 13, 1997, filed as a exhibit hereto and incorporated herein by 
reference.

Prior to June 1996, the Company believed, based on historical 
experience, that the production of successful, profitable analog and 
mixed signal products was less dependent on state-of-the-art 
semiconductor wafer fabrication manufacturing technology than the 
production of memory or microprocessor products.  As a result, the 
Company's previous strategy for new manufacturing process capability, 
described as a "fast follower" strategy, had the adoption of new 
fabrication process capability lagging approximately one to two years 
after introduction elsewhere in the industry.  However, the rapid 
innovation in wafer fabrication process technology in recent years has 
enabled semiconductor manufacturers to develop fabrication processes 
which are capable of creating circuit path definitions substantially 
less than one micron in width.  This development created the capability 
of producing integrated circuits containing significantly more 
transistors with markedly increased integration and functionality.  
Consequently, the Company modified its analog and mixed signal product 
development strategy to more aggressively pursue higher levels of 
functional integration in these products.  

This development led to the need for a revised fabrication process 
development plan in the first half of fiscal 1997 which matched the 
Company's product strategy with recent improvements in process 
capability.  As a result, the Company decided to aggressively develop 
its own state-of-the art, sub-micron wafer fabrication capability and to 
accelerate completion of its new 8-inch manufacturing facility in South 
Portland, Maine. In the third quarter of fiscal 1997, management began 
an evaluation of the Company's existing manufacturing process portfolio 
with the intent to rationalize existing wafer fabrication manufacturing 
capabilities in light of the strategy to produce more complex, highly 
integrated products on state-of-the-art fabrication processes.  

Based on this evaluation the Company determined that its rapid 
advancement of process capability would cause previously developed 
processes to be bypassed or become underutilized in the near future.  
Accordingly, management has made a number of decisions to realign the 
Company's wafer fabrication manufacturing capability in order to reduce 
costs, rationalize the number of production flows and consolidate 

manufacturing activities.  These actions are summarized in the press 
release dated May 13, 1997 filed as an exhibit hereto and incorporated 
herein by reference.  These actions will impact the following four 
manufacturing sites as described further below.

Arlington, Texas:

The Company has decided to cancel further investment in its 6-inch .65 
micron wafer fabrication expansion that had begun in 1995.  Under the 
"fast follower" strategy, the .65 micron process would have been the 
Company's most prevalent advanced manufacturing process available for 
use in the late 1990's.  However, the accelerated investment in the 8-
inch wafer fabrication facility in Maine will result in the availability 
of .35 micron capacity sooner than previously expected, allowing the 
Company to bypass the .65 micron generation of capacity.  The .65 micron 
fabrication expansion began in 1995 with an approved investment in 
facilities and equipment of $293 million and was expected to provide an 
estimated capacity of 18,000 six-inch wafer starts per month when fully 
completed.  The Company has expended approximately $128 million to date 
on the facility which is currently equipped to produce 4,000 wafer 
starts per month and is in the process of being qualified for 
production.  The decision to stop further investment in the .65 micron 
wafer fabrication facility has caused the Company to review the related 
assets for impairment.  The Company has therefore concluded that these 
assets are impaired and that a reduction to the carrying value of the 
assets in the amount of approximately $60 million is required by 
Statement of Financial Accounting Standards No. 121, "Accounting for the 
Impairment of Long-Lived Assets and for Long-Lived Assets to Be Disposed 
Of."  

The Company intends to hold the assets and continue to utilize the 
investment in these assets by ramping production in the fab line to 
4,000 wafer starts per month in fiscal 1998.  Since the wafer fab line 
in question is one of three production lines within the Company's 
existing Arlington facility, it is not practical to obtain quoted market 
prices in order to ascertain the fair value of the assets.  The fair 
value of the assets was estimated by comparing the future cash flows 
expected to be obtained from the assets to the carrying value of the 
assets. The expected future cash flows were less than the carrying value 
of the assets, resulting in asset impairment.  Accordingly, the Company 
will take a charge of approximately $60 million in the fourth quarter of 
fiscal 1997 to write-down the book value of the assets to the present 
value of the expected future cash flows from the wafer fab assets.  

Santa Clara, California:

The Company has decided to close its 5-inch and 6-inch wafer fabrication 
facilities and transfer their production activities to existing 
manufacturing lines in Greenock, Scotland and Arlington, Texas.  These 
two wafer fabrication lines are being closed to achieve cost savings and 
higher utilization of existing manufacturing lines in other Company 
facilities.  The closure process will take place over the next 15 
months.  The exit costs associated with closure are expected to be 
between $9 million and $11 million dollars.  The exit costs are 

primarily related to severance costs, the removal of production 
equipment and the dismantling and cleanup of the production facility.  
The Santa Clara 5-inch and 6-inch fabs currently employs about 500 
employees who will be offered opportunities to transfer to other Santa 
Clara operations, to relocate to other manufacturing locations or given 
severance packages.  The Company does not expect to place the majority 
of the affected employees elsewhere in the organization.

Greenock, Scotland:

The Company has also decided to halt its recent investment in the 
expansion of its 6-inch analog wafer fabrication line and will realign 
staffing at the 6-inch line in Scotland in order to match the capacity 
and cost structure of this facility to expected demand.  The decision to 
halt the expansion of this wafer fab will result in an asset write-off 
of approximately $4 million of previously capitalized construction in 
progress costs. The Company expects to also incur approximately $4 to $5 
million in charges for employee related costs.

Ft. Collins, Colorado:

The Company has decided to discontinue manufacturing, primarily hybrid 
assembly, at its Comlinear subsidiary operations located in Ft. Collins, 
Colorado, within the next six to twelve months.  This will result in a 
fourth quarter charge of approximately $3 million to $4 million for 
costs related to the exit plan.  The exit costs will be primarily 
comprised of severance costs and costs associated with contractual 
commitments which continue beyond the exit date.

In addition to the costs identified in the preceding paragraphs, the 
Company will incur other costs associated with these actions including 
stay-on bonuses and other manufacturing expenses that will be expensed 
to operations as incurred over the twelve to fifteen months in which the 
actions will occur.

Item 7. Financial Statements and Exhibits
- -----------------------------------------

    (c). Exhibits
         --------

    Designation of 
    Exhibit         Description of Exhibit
    --------------  ----------------------

         99         Contents of News Release dated  May 13, 1997.





SIGNATURE
- ---------

   Pursuant to the requirements of the Securities Exchange Act of 1934, 
the registrant has duly caused this report to be signed on its behalf by 
the undersigned thereunto duly authorized.



                                     NATIONAL SEMICONDUCTOR CORPORATION



Date:  May 14, 1997
                                     /S/  RICHARD D. CROWLEY, JR.
                                     -----------------------------------
                                     Richard D. Crowley, Jr.
                                     Vice President and Controller
                                     Signing on behalf of the registrant
                                     and as principal accounting officer





Exhibit 99                                      NEWS RELEASE

NATIONAL SEMICONDUCTOR ANNOUNCES

For more information:

P.R.: Bill Callahan             or       Alan Bernheimer
      (408) 721-2871                     (408) 721-8665
      bill.callahan @nsc.com             alan.bernheimer @nsc.com


Financial: Jim Foltz
(408) 721-5693
invest@nsc.com


NATIONAL ANNOUNCES REALIGNMENT OF MANUFACTURING 
WITH ONE TIME CHARGE OF $75-85M, OFFSET BY CREDITS OF $278M

Santa Clara, CA, May 13, 1997 - National Semiconductor Corporation 
(NSM:NYSE) today announced a comprehensive realignment of its 
manufacturing facilities, designed to accelerate its production 
transition to manufacturing 8-inch wafers with 0.35-micron circuit 
geometries, reduce costs and rationalize production flows. 
     To cover the cost of this program, National will take a one-time 
charge of $75 to $85 million in the fourth quarter, ending May 25, 1997. 
The action follows the completion of the previously announced sale of 
the company's former Fairchild Semiconductor business unit which 
resulted in a one-time credit of $278 million to pre-tax income. The 
credit represents a $77 million gain on the sale of Fairchild plus a 
$201 million reversal of the valuation allowance and other accruals 
related to the sale recorded in the first quarter of this fiscal year.
     "This realignment is another step in the pursuit of one of 
National's three strategic initiatives to become a world class 
manufacturing company, as we transition to provide system on a chip 
solutions for our key data highway partners, exploiting our analog 
expertise as a starting point for forward integration," said Kamal K. 
Aggarwal, executive vice president of National's Central Technology and 
Manufacturing Group.
     Approximately $60 million of the charge relates to the write down 
of certain assets in the Arlington, Texas wafer manufacturing plant, 
which have become impaired as defined by Financial Accounting Standard 
121. The remainder of the charge covers exit costs relating to closure 
of the company's 5- and 6-inch wafer fabs at its Santa Clara, California 
headquarters and smaller provisions for actions at other manufacturing 
facilities. 
     Products currently manufactured in these two Santa Clara fabs will 
be transferred to National's sites in Arlington, Texas and Greenock, 
Scotland over the next 15 months. The Santa Clara 5- and 6-inch fabs 
currently employ about 500 employees who will be offered opportunities 
to transfer to other Santa Clara operations, to relocate to other 
manufacturing locations or be given severance packages.
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