Foundry Agreement

EX-10.16 23 dex1016.htm FOUNDRY AGREEMENT Foundry Agreement

EXHIBIT 10.16

NOTE: Portions of this Exhibit are the subject of a Confidential Treatment Request by the Registrant to the Securities and Exchange Commission (the “Commission”). Such portions have been redacted and are marked with a “[***]” in the place of the redacted language. The redacted information has been filed separately with the Commission.

FOUNDRY AGREEMENT

THIS FOUNDRY AGREEMENT (this “Agreement”) is made as of January 10, 2002 (the “Effective Date”) by and between Hua Hong NEC Electronics Company Limited, a company incorporated under the laws of the People’s Republic of China (the “PRC”), whose principal offices is at No. 1188 Chuan Qiao Road, Pu Dong New District, Shanghai, China (“HHNEC”); and Alpha and Omega Semiconductor Limited, a company incorporated under the laws of Bermuda, whose registered office is at 479 East Evelyn Avenue, Sunnyvale, CA 94086, USA (“AOS”).

RECITALS

A.	AOS wishes HHNEC to manufacture power double diffused metal oxide semiconductor (“*DMOS*’) products for AOS.

B.	HHNEC has agreed to manufacture such products for AOS on the terms and conditions hereinafter contained.

C.	The parties intend: (i) that the relationship established hereunder shall be a long-term strategic partnership; and (ii) to use their best efforts to ensure the success of the tasks contemplated hereunder in a timely and successful fashion.

NOW, THEREFORE, the parties agree as follows:

1.	DEFINITIONS

The following capitalized terms shall have these meanings ascribed to them:

1.1 “Designs” means all masks, reticles, designs, test tapes, data base tapes, data, information and technical and other expertise relating to the manufacture of Products, each embodied in whatever appropriate form to enable HHNEC to set up the Process and to manufacture the Products.

1.2 “Die” means an individual functioning power DMOS device on a Wafer produced by HHNEC for AOS in accordance with the Specification using the Process.

1.3 “GDS” means “Graphic Design System” format, a mask file format in binary for integrated circuit masks.

1.4 “Intellectual Property Rights” means all patents, utility models, design rights, copyrights, semiconductor and mask work rights, trademarks and trade names, trade secrets, inventions (whether patentable or not), process technology, know-how, and all other intellectual property rights as may be recognized in any jurisdiction in the world as well as any applications and registrations for any of the foregoing.

1.5 “Lot” means a batch of Wafers: a Lot may be an “Engineering Lot,” “Qualification Lot” or a “Production Lot” for engineering, qualification and production purposes, respectively.

1.6 “Order” has the meaning set forth in Section 3.2.1.

1.7 “Process” means the process architecture, process flow, and unit module processes as a whole for the manufacture of Wafers, including but not limited to the integrated flow of such unit module processes, the specific sequence of such unit module processes, the masks and parameters for such unit module processes, the test protocol, procedures and parameters in connection with such unit module processes; provided that no such individual unit module process is a HHNEC Unit Module Process.

1.8 “Products” either Wafers or Dies.

1.9 “Qualification” means the testing of Products in accordance with the Specification and the Qualification Criteria, with the objective of approving of the Process by AOS as being ready for production of the Products.

1.10 “Qualification Criteria” means the criteria set forth in Schedule 3, part 1.

1.11 “HHNEC Unit Module Process” means any individual unit module process that is either in existence as of the Effective Date or solely developed by HHNEC during the Term for setting up and integration with the Process, including but not limited to the test protocols, procedures and parameters in the connection therewith; provided that the foregoing shall not include any mask layers developed hereunder or GDS files provided by AOS.

1.12 “Specification” means the specification set forth in Schedule 2, part 2.

1.13 “Stop Notice” has the meaning set forth in Section 4.2.

1.14 “Term” has the meaning set forth in Section 9.1.

1.15 “Wafer” means the power DMOS devices manufactured pursuant to this Agreement in the form of 8 inch silicon wafers.

1.16 “Wafer Acceptance Criteria” means the criteria for acceptance of the Wafers as forth in Schedule 4, part 1, which criteria may be amended in writing by both parties hereto.

2.	ENGINEERING; QUALIFICATION

2.1 Designs, Process. AOS shall provide HHNEC with such part of the Designs and the Process as has been agreed between the parties in such form and in such detail as HHNEC shall reasonably require; provided, however, that:

2.1.1 Masks. AOS shall provide HHNEC with the mask Designs for the Product in GDS format. HHNEC shall select a mask-making vendor that is reasonably suitable as to quality, service and cost for converting the GDS mask design into masks suitable for the Process, as well as avoidance of time for any reworking. The Process will be 0.35 micron and use seven (7) masks/layers, with mask/layer variation subject to approval by AOS;

2.1.2 Substrate; Epitaxy. HHNEC shall be responsible for the substrate and epitaxy such that the substrate shall be: (i) 1-3 mW-cm for n-channel and 1-5 mW-cm for p-channel; (ii) grown by single epitaxial reactor to ensure tolerance and quality; and (iii) provided via a vendor chosen by HHNEC based on substrate quality and reactor availability. The parties shall jointly develop an effective method of: (a) securing the measurement correlation of epitaxy profiles; and (b) shortening the lead time of epitaxy delivery from vendors so as to speed up Product develop and manufacture;

2.1.3 Metrology. HHNEC shall be responsible for developing an effective method of measuring the depth of the narrow and deep trenches in the Wafers;

2.1.4 Back Metal. The back metal shall be: (i) ground to 200 microns; (ii) subjected to diluted hydrofluoride (HF) treatment before metal deposition; (iii) composition of either Ti-Ni-Ag or Cr-Au; and (iv) deposited via a refurbished metal system processor purchased by HHNEC;

2.1.5 Defects Gettering. HHNEC shall use dichloroethylene (DCE) or hydrochloride (HCl) in two (2) furnaces to assure overall product integrity; and

2.1.6 N & P Process Flows. The preliminary process flows for n and p-channels, based on HHNEC’s fab ability, has already been provided to HHNEC and is subject to revision by the parties.

2.2 Set-up and Qualification. HHNEC shall begin the work to set up and qualify the Process, and the development and implementation of any necessary HHNEC Unit Module Process, the design and execution of short-loop experiments to develop and build up process blocks (with or without masks), and the manufacture and delivery of Product prototypes and Engineering Lots. AOS shall reasonably cooperate with HHNEC with setting up and qualifying the Process. HHNEC shall be responsible for obtaining, setting up and maintaining all equipment that conform to the Specification and are necessary for the development and manufacture of the Products, including the immediate ordering of necessary process equipment, such that such equipment will be delivered to HHNEC in accordance with the schedules for equipment/unit step set up, and for Product set up and release, as set forth in Schedule 1, Parts 1 and 2, respectively.

2.3 Testing. HHNEC will provide the first Die sort tester and all probers; it shall be AOS’ responsibility for any additional Die sort testers required hereunder. The parties shall use commercially reasonable efforts to reduce the need for full testing after production of Products is stabilized, as demonstrated by yield enhancement.

Both sides assign a dedicated person to form a task force to realize cost reduction through yield management to minimize test cost(such as sampling test as a goal.).

2.4 Engineering Lots. HHNEC shall manufacture and deliver Engineering Lots to AOS in accordance with Schedule 3, part 2, with copies of all relevant test data sheets. During the engineering and Qualification phase, HHNEC shall provide AOS with results of PCM (Process Monitor), CP (Chip Probe) test, die-sort test and in-line monitor testing of every Lot as a partial progress report leading to the outgoing visual inspection specification. As soon as practicable after AOS’ testing of the Engineering Lots, AOS shall provide HHNEC a status update via electronic communications means. If AOS notifies HHNEC that any Wafers in an Engineering Lot are misprocessed for reasons attributable to HHNEC, HHNEC shall at its own expense use commercially reasonable efforts to rerun the Wafers and resubmit Wafers meeting the Specification and the Qualification Criteria. Before release to production, each Product shall fully meet the Qualification Criteria.

2.5 Visits. During the Term, AOS may assign one (1) engineer for up to two (2) years to work at the sites and facilities of HHNEC, to discuss, assist and facilitate the Process and production set up. Such engineer shall observe all HHNEC regulations.

3.	MANUFACTURING; ROLLING FORECAST; ORDER AND SUPPLY; CYCLE TIME; EXCLUSIVITY

3.1 Forecasts. Once the Process is set up and stabilized at HHNEC, AOS will provide to HHNEC in writing a rolling forecast of its Orders for Wafers on a six-month forward basis on or before the 15th of each month. The first-month estimate of each such forecast will be a firm estimate, the second-month estimate will allow 30% variation therefrom, the third-month estimate will allow 60% variation therefrom, and the estimates for the fourth through sixth months will be for reference as a good faith estimate only.

3.2 Orders.

3.2.1 Placement. On or about 20th of each month after providing the first rolling forecast pursuant to Section 3.1, and at such other times as deemed necessary by AOS; AOS may place an order for one or more Production Lots with HHNEC in writing (an “Order”).

3.2.2 Acceptance. Within three (3) business days of receipt of an Order, HHNEC shall notify AOS in writing, either to acknowledge the acceptance of such Order, or to provide the reason why such Order is not accepted, or to suggest the way in which HHNEC wishes to modify such Order. An Order placed by AOS in accordance herewith shall be deemed accepted by HHNEC absent a timely notice in writing of non-acceptance or modification. HHNEC shall manufacture and supply the Products in accordance with any and all Orders accepted by HHNEC.

3.2.3 Order Changes. No Order placed by AOS and accepted by HHNEC may be unilaterally changed by either party, with the exception that: (i) AOS may change the date of delivery to a later date by notifying HHNEC in advance; or (ii) AOS may cancel such an Order or reduce the quantity of the Products under such an Order, subject to Section 5.1.

3.2.4 Capacity Commitment. HHNEC shall make its best efforts to: (i) ramp up Production Lots (“Production Start”) within three (3) months of the first Qualification of Product; (ii) accommodate 1,695 Wafers per month in the first twelve (12) months after production start; (iii) accommodate 3,955 Wafers per month in the next twelve (12) months; (iv) accommodate 6,214 Wafers per month in the next twelve (12) months after that and at least such volume thereafter (and increase in line with market growth); and (v) accommodate volumes of Wafers that differ from the foregoing by -30% to +50%. HHNEC shall reserve and provide capacity to meet the foregoing requirements.

3.3 Cycle Time. HHNEC shall use its best efforts to ensure that Qualification and Production Lots cycle time shall be no more than 2 days per layer, plus 6 days allowance for backside metal, die sort, packaging and paperwork. In the event that HHNEC fails to meet such cycle times, then HHNEC shall use its best efforts to solve the problem causing such failure, and AOS shall upon request provide reasonable assistance to help HHNEC solve such problem.

3.4 HHNEC Testing. HHNEC will promptly notify AOS in writing after discovery of any defect or non-conformity in either the Products already shipped to AOS or Wafers currently being processed for AOS.

3.5 Cost Reductions. HHNEC and AOS shall each use its commercially reasonable effort to reduce the cost of the Wafers. HHNEC and AOS shall share equally any such reduction in cost.

3.6 Records; Reports; ECNs. HHNEC shall keep records of all production control information and summaries of production monitors for a period of five (5) years from the date of production, and shall at the request of AOS forward to AOS a copy of such data. HHNEC shall provide to AOS, upon AOS’ written request during the Term and for three (3) years thereafter, various reports listed in Schedule 4, part 3. Any engineering change notice (“ECN”) initiated by HHNEC on engineering or specification change in HHNEC should be approved by AOS in writing prior to the implementation of such change. The obligations of HHNEC under this Section 3.6 shall include but not limited to process or equipment change, bill of material, quality inspection or monitoring procedures or specifications.

3.7 Exclusivity. HHNEC agrees that, during the term of this Agreement or five (5) years from the Effective Date, whichever is longer, it will not enter into any agreement for production, supply and/or service related to any DMOS products with any customer except AOS. HHNEC represents and warrants that the execution and delivery of this Agreement and performance under this Agreement will not in any aspect interfere with or be impeded by any agreement, understanding or relationship between HHNEC (including its affiliates) and its current customers (including their affiliates).

4.	DELIVERY; ACCEPTANCE AND STOP NOTICE; QUALITY DATA; RMA

4.1 Delivery. All the Products shall be vacuum sealed supplied FOB Shanghai. Delivery of the Products shall take place when HHNEC has handed over the Products, cleared for export, into the charge of a carrier named by AOS. Risk and title in the Products shall pass to AOS upon such delivery. AOS shall acknowledge to

HHNEC the receipt of each shipment of the Products stating quantity, type, and shipment damages existing at delivery, within thirty (30) days of receipt at AOS’s destination. HHNEC shall not be responsible for any claims relative to quantity and shipment damages made after the foregoing thirty (30) day period. AOS may decline to accept any Products, in its discretion, that are not delivered within the cycle time specified in Section 3.3. HHNEC may, for the purpose of assuring timely delivery of the Products to AOS and subject to reasonable approval by AOS, maintain up to one (1) month inventory of Products (per the rolling forecast provided by AOS in accordance with Section 3.1).

4.2 Final Testing. AOS shall perform final testing of the Products after assembly of the Products. In the event that any Product fails such final tests, where AOS reasonably suspects the corresponding Wafers delivered would have failed to pass the Wafer Acceptance Criteria, AOS may immediately issue a stop notice, upon receipt of which HHNEC shall immediately stop manufacture and/or shipment of the affected Wafers (a “Stop Notice”).

4.3 Effect of Stop Notice. If HHNEC is responsible for a failure necessitating a Stop Notice and is unable to correct the matter within thirty (30) days of receipt of such Stop Notice, AOS may: (i) reject any non-conforming Products or Wafers; and/or (ii) cancel any then-pending Orders for such Wafers without payment or penalty. If AOS issues a Stop Notice for any Wafers which AOS is obligated to purchase, and such Wafers are later determined by HHNEC and AOS to pass the Wafer Acceptance Criteria, then AOS shall pay HHNEC in full for completed Wafers and, in addition, for HHNEC’s reasonable costs for work in progress.

4.4 RMAs. AOS may make any returns to HHNEC with a written return material authorization (“RMA”) issued by HHNEC. HHNEC will analyse such authorised returns and report to AOS on the results of such analysis within thirty (30) days of receipt of such RMA. AOS will cooperate with HHNEC to resolve any problems associated with the returns. If AOS and HHNEC determine that any Products returned under an RMA are defective for reasons attributable to HHNEC, HHNEC shall immediately refund any payment made by AOS for such Products and reimburse AOS for assembly and testing costs related to such Products.

5.	PAYMENT

5.1 Prices. The prices for the Wafers are as set forth in Schedule 4, part 2; provided, however, that in the event of an Order change per Section 3.2.3, AOS shall pay such prices in full for all Wafers fifty percent (50%) or more of the mask layers of which have been processed and fifty percent (50%) of such prices for all Wafers less than fifty percent (50%) of the mask layers of which have been processed.

5.2 Payment Terms. HHNEC shall invoice AOS after delivery of the Products and AOS shall pay all sums due in US dollars by telegraphic transfer within sixty (60) days of receipt of any undisputed invoice.

6.	INTELLECTUAL PROPERTY RIGHTS

6.1 AOS. All Intellectual Property Rights in and to the Designs, the Process the Products (and related masks and GDS files) including all revisions, modifications and improvements respectively thereto, whether made or supplied by AOS or developed jointly by AOS and HHNEC, shall be solely and exclusively owned by AOS, subject only to a license to HHNEC (and not any third party including HHNEC affiliates) to manufacture the Products for AOS pursuant to this Agreement. Any documentation provided by AOS to HHNEC hereunder, fixed in whatever appropriate form, and any Intellectual Property Rights associated therewith, shall belong solely and exclusively to AOS.

6.2 HHNEC. Subject to the provisions of Section 6.1, all Intellectual Property Rights in and to the HHNEC Unit Module Processes, including all revisions, modifications and improvements thereto, shall be solely and exclusively owned by HHNEC, subject only to a license to AOS to use, import/export, and sell or otherwise dispose of the Products.

6.3 Cooperation. Each party agrees to take such further action and execute, or cause its employees, agents and contractors to execute, such further instruments as may be necessary to give effect to the ownership provisions of this Agreement.

7.	CONFIDENTIALITY

7.1 Scope. With respect to any and all information, whether oral, written or visual, disclosed or provided pursuant to or in connection with this Agreement in whatever format, including without limitation the Designs, the Process and the HHNEC Unit Module Processes (the “Confidential Information”), each party shall keep the other party’s Confidential Information strictly secret and confidential, shall not use the same other than for the purposes of this Agreement, and shall disclose the same only on a need-to-know basis to those of its full-time employees, and contractors expressly contemplated hereunder who are subject to confidentiality agreements. Other than as provided by the foregoing, one party’s Confidential Information shall not be disclosed to third parties (including the other party’s affiliates).

7.2 Exceptions. For purposes hereof, Confidential Information shall not include information: (i) was already known to the receiving party without an obligation of confidentiality at the time of disclosure hereunder; (ii) was generally available to the public at the time of its disclosure to the receiving party hereunder; (iii) became generally available to the public after its disclosure other than through an act or omission of the receiving party in breach of this Agreement; (iv) was subsequently, lawfully and independently disclosed to the receiving party by a person other than the Disclosing Party, not in violation of the confidentiality agreement, arrangement or understanding with such person; or (v) is required to be disclosed pursuant to applicable law, provided that the disclosing party is provided reasonable notice and opportunity to contest the need for such disclosure, or to seek a protective order therefor.

7.3 Publicity. Neither AOS nor HHNEC shall disclose the existence or terms of this Agreement to any third party without the prior written consent of the other party, except as required by applicable laws; provided, however, that the parties shall issue a joint press release about the relationship hereunder promptly after execution of this Agreement.

7.4 Injunctive Relief. Each party acknowledges that unauthorized disclosure or use of the Confidential Information of the other party may cause irreparable harm to the other party for which recovery of money damages would be inadequate, and the other party shall therefore be entitled to obtain timely injunctive relief to protect its rights under this Agreement, in addition to any and all remedies available at law.

7.5 Prior NDA. AOS and HHNEC Parties have entered into a nondisclosure agreement dated August 20, 2001, which is hereby superseded in its entity for purposes of this Agreement.

8.	WARRANTIES AND LIABILITY; INDEMNIFICATION

8.1 Warranties. HHNEC warrants that all Wafers delivered to AOS shall: (i) be processed using the masks which have been approved by AOS or to the extent there have been changes, such changes have been approved by AOS in ECN format; (ii) be within the process parameter tolerances stated in the Process; (iii) at the date of delivery conform to the Specifications and shall be free from defects in workmanship and materials; and (iv) for one year from the date of shipment, be free from defects in material and workmanship provided that such Wafers will be vacuum sealed or stored in a controlled nitrogen environment or dry air environment with relative humidity 40-50% and temperature 23-28°C. To the extent that any Products fail to meet the foregoing warranties and/or requirements due to reasons for which HHNEC is responsible, HHNEC shall either: (a) replace such Wafers without charge; or (b) refund the payments made to HHNEC for such Wafers, as the case may be, within thirty (30) calendar days of HHNEC’s receipt of written notice from AOS of such non-conformity.

8.2 Disclaimer. IN NO EVENT SHALL EITHER PARTY BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE OR SPECIAL DAMAGES, OR FOR LOSS OF PROFITS, LOSS OF USE OF

DATA, OR INTERRUPTION OF BUSINESS, WHETHER SUCH DAMAGES ARE ALLEGED IN TORT, CONTRACT OR INDEMNITY, EVEN IF SUCH PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THIS LIMITATION OF LIABILITY SHALL NOT APPLY TO DAMAGES ASSOCIATED WITH (I) THE INFRINGEMENT OR UNAUTHORIZED USE OF INTELLECTUAL PROPERTY RIGHTS AND (II) THE BREACH OF OBLIGATIONS UNDER SECTIONS 6 OR 7 HEREOF.

8.3 Indemnification. AOS shall indemnify, defend, and hold HHNEC harmless from and against any and all liabilities, damages, losses, claims, costs and expenses (including reasonable attorneys’ fees) (“Claims”) resulting from the infringement of any third-party Intellectual Property Rights by HHNEC’s making the Wafers in compliance with the Designs and the Process at HHNEC’s sites and facilities. HHNEC shall indemnify, defend, and hold harmless AOS from and against any and all Claims resulting from the infringement of any third-party Intellectual Property Rights by the use of any HHNEC Unit Process Module and from any property damage or bodily injury (including death) of HHNEC’s employees, agents, contractors, consultants or representatives out of performance of this Agreement. In either case, the indemnified party shall promptly notify the indemnifying party of a Claim, allow the indemnifying party to take sole control of the defense and settlement of the Claim, and provide the indemnifying party with all reasonable information, assistance and authority, at the indemnifying party’s expense.

9.	TERM AND TERMINATION

9.1 Term. This Agreement shall commence on the Effective Date and shall, subject to Section 9.2, continue in force for an initial Term of five (5) years. The parties in good faith contemplate a renewal for a subsequent Term of five (5) years thereafter.

9.2 Termination. If either party (the “Defaulting Party”) defaults in the performance of any material provision of this Agreement and fails to cure such default within thirty (30) days after receiving a written notice from the other party (the “Terminating Party”), then the Terminating Party may, in addition to any other remedies it may have, terminate thereupon this Agreement by giving written notice of termination to the Defaulting Party.

9.3 Effect of Termination. Upon termination or expiration of this Agreement, Sections 1, 3.6, 3.7, 5.2, 10.2, 6, 7, 8, 9.3 and 10 shall remain in full force and effect in accordance with their respective terms, and each party shall return to the other party all Confidential Information of the other party in its possession or under its control. Unless HHNEC is the Defaulting Party under Section 9.2, all payments still owed HHNEC at termination or expiration shall be due and payable in full immediately. Unless AOS is the Defaulting Party under Section 9.2, Section 4.4 shall also remain in full force and effect after the termination of this Agreement.

10.

GENERAL

10.1 Notices. Any notice required to be given by either party hereunder shall be in writing and served personally or sent by Federal Express or facsimile addressed to the other party at the address or facsimile number set forth below unless such address or number is changed by written notice for this purpose:


HHNEC: Hua Hong NEC Electronics Company Limited		AOS: Alpha and Omega Semiconductor Limited

Address:	No. 1188 Chuan Qiao Road, Pu Dong New District, Shanghai, China	Address:	479 East Evelyn Avenue Sunnyvale, CA 94086, USA

To the attention of: Toshio Ohta, Exec. Vice President		To the attention of: Mike Chang, President

Facsimile No. 011 (8621) 5834-4909		Facsimile No.: 1 (408) 830-9749

Any notice served personally shall be deemed to have been given on such service. Any notice sent by Federal Express shall be deemed to have been served 72 hrs after the same have been posted or delivered to carrier. Any notice given by facsimile shall be deemed to have been served 24 hrs after the time of transmission (as corroborated by a facsimile transmission report).

10.2 Governmental Approval. Upon reasonable request from AOS, HHNEC shall assist AOS in obtaining governmental approval or clearance for operations, logistics, import/export and tax aspects relating to the transfer of Wafers from HHNEC to the assembly house in the PRC.

10.3 Assignment. Neither party may assign, delegate, transfer or otherwise dispose of any rights or obligations under this Agreement in part or in whole without the prior consent of the other; provided, however, that: (i) either party may assign and transfer this Agreement as part of the sale of all or substantially all of its equity or assets as part of a merger, acquisition or sale; and (ii) the resulting or acquiring entity agrees to abide by the terms of this Agreement.

10.4 Independent Contractors. The status of the parties is one of independent contractors and nothing contained in this Agreement shall be construed or interpreted as creating any agency or partnership. Neither party has the right or authority to assume, create or incur liability of any kind against or on behalf of the other.

10.5 Waivers. Any reasonable forbearance or reasonable delay on the part of either party in enforcing the provisions of this Agreement or any of its rights hereunder shall not be construed as a waiver of such provisions or rights and shall in no way affect such parties the right to later enforce such provision.

10.6 Force Majeure. No Party shall be liable in any manner for failure or delay upon fulfillment of all or part of this Agreement, directly or indirectly owing to any cause beyond its reasonable control, including, but not limited to, acts of God, governmental orders or restriction, war, threat of war, warlike conditions, strike, lockout, interruption of transportation or inability to obtain necessary labor, materials, or facilities. However, if HHNEC cannot supply the Wafers, AOS may seek other sources of supply and reduce the amount it has committed to buy from HHNEC. HHNEC shall notify AOS at the earliest indication of any interruption in supplying the Wafers or other facility difficulty, which may impact the availability of Wafers or Products under this Agreement.

10.7 Severability. The invalidity or unenforceability for any reason of any part of this Agreement shall not prejudice the continuance in force of the remainder.

10.8 Governing Law; Arbitration. This Agreement shall be governed by and construed in all respects in accordance with the laws of California. Any dispute or claim arising out of or in connection with this Agreement or the performance, breach or termination thereof, shall be finally settled by binding arbitration in Singapore, under the Rules of Arbitration of the International Chamber of Commerce by three arbitrators appointed in accordance with such rules. Judgment on the award rendered by the arbitrators may be entered in any court having jurisdiction thereof; provided, however, that either party may apply to any court of competent jurisdiction for injunction relief to enforce Section 7.4.

10.9 Entire Agreement; Modifications. This Agreement together with its Schedules embodies the entire and complete understanding of the parties in relation to this subject matter and overrides or supersedes all prior promises, agreements, understandings, proposals and representations and warranties made by either party with respect to this subject matter. This Agreement may be varied, changed, modified or amended in writing signed by a duly authorized representative of each party.

IN WITNESS whereof, the parties have caused this Agreement to be executed and delivered by their duly authorized representatives the day and year first above written.


Hua Hong NEC Electronics Company Limited			Alpha and Omega Semiconductor Limited

By:	/s/ Toshio Ohta 1/10/2002		By:	/s/ Mike Chang 1/10/2002
Name:		Toshio Ohta	Name:		Mike Chang
Title:		Executive Vice President	Title:		President

Schedule 1

Designs and Process

Part 1 - Schedule for Equipment/Unit Step Set Up


EPI Wafer Source Selection	42 days	12/13/01 8:00	2/8/02 17:00
Confirm quality/capability from Shinetsu	7 days	12/13/01 8:00	12/21/01 17:00
AOS provide correlation pieces to HHNEC for Shinetsu to do correlation measurement	5 days	12/17/01 8:00	12/21/01 17:00
Shinetsu to provide As doped substrate information details	5 days	12/13/01 8:00	12/19/01 17:00
AOS will determine order quantity based on matrix design	5 days	12/17/01 8:00	12/21/01 17:00
Order SEH wafers, p and n	35 days	12/24/01 8:00	2/8/02 17:00	2

Mask Making Procedure	24 days	12/13/01 8:00	1/15/02 17:00
Need a quote from Dupont ShangHai for different grade	5 days	12/13/01 8:00	12/19/01 17:00
View E-Beam Layout in San Jose, or alternative	5 days	12/13/01 8:00	12/19/01 17:00
AOS and HHNEC to confirm enough information for mask making	5 days	12/13/01 8:00	12/19/01 17:00
AOS to provide 1st set of Trench and metal mask information to HHNEC	10 days	12/13/01 8:00	12/26/01 17:00
To finish Trench and metal mask before 1/16/2002	15 days	12/26/01 8:00	1/15/02 17:00

DCE Implementation	36 days	12/31/01 8:00	2/18/02 17:00
HHNEC order DEC parts	25 days	12/31/01 8:00	2/1/02 17:00
Installation and process setup	10 days	2/5/02 8:00	2/18/02 17:00

Etch development with HHNEC’s test masks, results to AOS USA	26 days	12/20/01 8:00	1/24/02 17:00
Trench etch, Oxide mask and Resist mask	10 days	12/20/01 8:00	1/2/02 17:00
Round hole etch	10 days	1/3/02 8:00	1/16/02 17:00	20
Trench measurement by CDSEM capability confirmation, Top side down	3 days	1/2/02 8:00	1/4/02 17:00
Contact Isotropic etch	10 days	12/20/01 8:00	1/2/02 17:00
2.8 um metal dry etch	7 days	1/3/02 8:00	1/11/02 17:00	23
Gate oxidation/Poly Dep. Poly etchback	7 days	1/16/02 8:00	1/24/02 17:00

Backmetal Implementation	75 days	12/17/01 8:00	3/29/02 17:00
Grind down to 200 um	1 day	12/17/01 8:00	12/17/01 17:00
Si Stress release etch 4 um in SEZ	25 days	12/18/01 8:00	1/21/02 17:00	28
50:1 HF etch in SEZ	25 days	12/18/01 8:00	1/21/02 17:00
Backmetal evaporator delivery	50 days	12/17/01 8:00	2/22/02 17:00
Evaporator installation	10 days	2/25/02 8:00	3/8/02 17:00	31
Ti/Ni/Ag Evaporation Process setup	15 days	3/11/02 8:00	3/29/02 17:00	32

Trench Oxide Breakdown Test	62 days	12/17/01 8:00	3/12/02 17:00
To purchase substrate with notch @(100), n or n+	30 days	12/17/01 8:00	1/25/02 17:00
Establish breakdown test method, CV	5 days	12/17/01 8:00	12/21/01 17:00
Trench Oxode Breakdown Test, Notch must be @(100), no doping concern, n or n+, 2 pcs	10 days	2/18/02 8:00	3/1/02 17:00

B-penetration Test, after DCE is ready	62 days	12/17/01 8:00	3/12/02 17:00
Prepare lightly doped n-type (n-, 10-20 ohms) substrate, normal substrate	1 day	1/7/02 8:00	1/7/02 17:00
AOS design implant split table	1 day	12/18/01 8:00	12/18/01 17:00
Grow Gate oxide 250 A	1 day	3/4/02 8:00	3/4/02 17:00	17
Poly , undoped, 1.0 um	1 day	3/5/02 8:00	3/5/02 17:00	43


implant, P and B, split	1 day	3/6/02 8:00	3/6/02 17:00	44
Go through body and source drive (one wafer skip this process)	2 days	3/7/02 8:00	3/8/02 17:00	45
C-V dot patterning	1 day	3/11/02 8:00	3/11/02 17:00	46
Measure C-V curve @ room temperature	1 day	3/12/02 8:00	3/12/02 17:00	47

Testing set up	55 days	12/17/01 8:00	3/1/02 17:00
Purchase CATS 530	50 days	12/17/01 8:00	2/22/02 17:00
AOS provide N003 7 mohm samples (6”) wafers for equipment set up	5 days	2/25/02 8:00	3/1/02 17:00	51

*Part 2 - Schedule for Product Set Up and Release*
12/30V N_channel LS/NB	157 days	3/1/02 8:00	10/7/02 17:00
N01 1st Engineering lot	25 days	3/1/02 8:00	4/4/02 17:00
N01 2nd Engineering lot	25 days	4/9/02 8:00	5/13/02 17:00
N01 3rd Engineering lot	22 days	5/14/02 8:00	6/12/02 17:00	3
N01 4th Engineering lot	22 days	6/13/02 8:00	7/12/02 17:00	4
N01 Assembly	12 days	7/15/02 8:00	7/30/02 17:00	5
N01 Rel. Test 168hrs	12 days	7/31/02 8:00	8/15/02 17:00	6
N01 Rel. Test 500hrs	12 days	8/16/02 8:00	9/2/02 17:00	7
N01 Rel. Test 1000hrs	15 days	9/3/02 8:00	9/23/02 17:00	8
N01 5th Engineering lot	22 days	7/15/02 8:00	8/13/02 17:00	5
N01 Rel. Test 168hrs	12 days	8/14/02 8:00	8/29/02 17:00	10
N01 Rel. Test 500hrs	12 days	8/30/02 8:00	9/16/02 17:00	11
N01 Rel. Test 1000hrs	15 days	9/17/02 8:00	10/7/02 17:00	12
3 PP Lots, 25 each	25 days	8/14/02 8:00	9/17/02 17:00	10
Production	0 days	9/17/02 17:00	9/17/02 17:00	14

25/30 P-Channel Charger	155 days	3/1/02 8:00	10/3/02 17:00
P01 1st Engineering lot	25 days	3/1/02 8:00	4/4/02 17:00
P01 2nd Engineering lot	25 days	4/5/02 8:00	5/9/02 17:00	18
P01 3rd Engineering lot	22 days	5/10/02 8:00	6/10/02 17:00	19
P01 4th Engineering lot	22 days	6/11/02 8:00	7/10/02 17:00	20
P01 Assembly	12 days	7/11/02 8:00	7/26/02 17:00	21
P01 Rel. Test 168hrs	12 days	7/29/02 8:00	8/13/02 17:00	22
P01 Rel. Test 500hrs	12 days	8/14/02 8:00	8/29/02 17:00	23
P01 Rel. Test 1000hrs	15 days	8/30/02 8:00	9/19/02 17:00	24
P01 5th Engineering lot	22 days	7/11/02 8:00	8/9/02 17:00	21
P01 Rel. Test 168hrs	12 days	8/12/02 8:00	8/27/02 17:00	26
P01 Rel. Test 500hrs	12 days	8/28/02 8:00	9/12/02 17:00	27
P01 Rel. Test 1000hrs	15 days	9/13/02 8:00	10/3/02 17:00	28
3 PP Lots, 25 wfs each	25 days	8/12/02 8:00	9/13/02 17:00	26
Production	0 days	9/13/02 17:00	9/13/02 17:00	30

12/30V N-channel HS/NB	125 days	4/1/02 8:00	9/20/02 17:00
N02 1st Engineering lot	25 days	4/1/02 8:00	5/3/02 17:00
N02 2nd Engineering lot	25 days	5/6/02 8:00	6/7/02 17:00	34
N02 3rd Engineering lot	25 days	6/10/02 8:00	7/12/02 17:00	35
N02 Assembly	12 days	7/15/02 8:00	7/30/02 17:00	36
N02 Rel. Test 168hrs	12 days	7/31/02 8:00	8/15/02 17:00	37
N02 Rel. Test 500hrs	12 days	8/16/02 8:00	9/2/02 17:00	38
N02 4th Engineering lot	25 days	7/15/02 8:00	8/16/02 17:00	36
N02 Rel. Test 168hrs	12 days	8/19/02 8:00	9/3/02 17:00	40
N02 Rel. Test 500hrs	12 days	9/4/02 8:00	9/19/02 17:00	41


3 PP Lots, 25 wfs each	25 days	8/19/02 8:00	9/20/02 17:00	40
Production	0 days	9/20/02 17:00	9/20/02 17:00	43

12/20V N-Channel CD	125 days	5/1/02 8:00	10/22/02 17:00
N03 1st Engineering lot	25 days	5/1/02 8:00	6/4/02 17:00
N03 2nd Engineering lot	25 days	6/5/02 8:00	7/9/02 17:00	47
N03 3rd Engineering lot	25 days	7/10/02 8:00	8/13/02 17:00	48
N03 Assembly	12 days	8/14/02 8:00	8/29/02 17:00	49
N03 Rel. Test 168hrs	12 days	8/30/02 8:00	9/16/02 17:00	50
N03 Rel. Test 500hrs	12 days	9/17/02 8:00	10/2/02 17:00	51
N03 4th Engineering lot	25 days	8/14/02 8:00	9/17/02 17:00	49
N03 Rel. Test 168hrs	12 days	9/18/02 8:00	10/3/02 17:00	53
N03 Rel. Test 500hrs	12 days	10/4/02 8:00	10/21/02 17:00	54
3 PP Lots, 25 wfs each	25 days	9/18/02 8:00	10/22/02 17:00	53
Production	0 days	10/22/02 17:00	10/22/02 17:00	56

20/30V N-Channel, HS/MB	125 days	6/3/02 8:00	11/22/02 17:00
N04 1st Engineering lot	25 days	6/3/02 8:00	7/5/02 17:00
N04 2nd Engineering lot	25 days	7/8/02 8:00	8/9/02 17:00	60
N04 3rd Engineering lot	25 days	8/12/02 8:00	9/13/02 17:00	61
N04 Assembly	12 days	9/16/02 8:00	10/1/02 17:00	62
N04 Rel. Test 168hrs	12 days	10/2/02 8:00	10/17/02 17:00	63
N04 4th Engineering lot	25 days	9/16/02 8:00	10/18/02 17:00	62
N04 Rel. Test 168hrs	12 days	10/21/02 8:00	11/5/02 17:00	65
3 PP Lots, 25 wfs each	25 days	10/21/02 8:00	11/22/02 17:00	65
Production	0 days	11/22/02 17:00	11/22/02 17:00	67

AOS CONFIDENTIAL

Schedule 2

Part 1 - Products

AOS will provide regular updates as Design(s) are developed.

Part 2 - Specifications

AOS will provide Specifications during engineering phase for each Product.

Schedule 3

Part 1 - Qualification Criteria

All tests on selected parameters must meet Specifications.

Products must pass 168 hours, 500 hours and 1000 hours of HTGB and HTRB reliability tests. AOS with the help from HHNEC will actively perform failure analysis to identify cause and to eliminate the cause for fast introduction of production.

The sampling die sort (the “CP” test) must pass the “Yield Limit”, which is defined as the average of CP yields of three (3) Engineering Lots each having a minimum of twelve (12) Wafers.

The Yield Limit shall be the “Agreed Production Yield”.

HHNEC implements ECN for all of the qualified masks and processes.

HHNEC implements ECN for the outgoing visual inspection specification.

HHNEC sets up in-line SPC monitor systems.

Part 2 - Engineering Lots

Minimum Engineering Lot Size: Six (6) Wafers.

Cost per Engineering Lot Wafer: [***].

Engineering Lots can be staged at any step of the Process.

***CONFIDENTIAL PORTIONS OMITTED AND FILED SEPARATELY WITH THE COMMISSION***

Schedule 4

Part 1 - Wafer Acceptance Criteria

All tests of PCM parameters must pass Specifications.

All wafers must pass the outgoing visual inspection specification.

No diffusion or thin film rework is allowed.

The acceptance yield limit will be the Agree Production Yield minus two (2) sigmas as a reference for the time. Finalized form will be achieved one month after production.

The scrap limit will be determined jointly later according to reliability concerns of AOS’s customers.

Wafers below the acceptance yield limit may be accepted by AOS at prices discounted according to the deficiencies. AOS may decline to accept any such wafers if it determines that such wafer poses a threat to its customer’s product reliability.

Part 2 - Orders and Prices

Minimum Production Lot Size: Twenty-five (25) Wafers.

Prices (based on 0.35 µm DMOS Wafers with seven (7) mask layers that includes wafer processing, PCM test, CP test, die-sort test; epitaxyl layer and silicon substrate): [***]

Prices above will be adjusted, for Wafers having other than seven (7) mask layers, by [***] per mask layer that differs from 7 layers

Part 3 - Reports

Every two day work in progress (“WIP”) report through electronic means by HHNEC.

PCM, CP and die-sort test data for every Lot.

Monthly in-line SPC, outgoing visual inspection, and oxide V-ramp reports.

Electrical and mechanical yield reports.

***CONFIDENTIAL PORTIONS OMITTED AND FILED SEPARATELY WITH THE COMMISSION***